std-match initially mentioned the fact, that some design compilers, that are referring to an old VHDL version, allow buffer ports to be only connected to type buffer in the upper hierarchy. This isn't however required by recent tools as far as I'm aware of, e.g. Altera Quartus doesn't require it since ever, also ModelSim doesn't. They even tolerate, that the buffer property is hidden in a component definition in an upper entity by renaming a buffer to out.
Functionally, there's no difference between buffer and a temporary signal usage for output ports, presuming the assignment of temporary signal to output signal is done in concurrent code.
I also didn't hear, that in Verilog, where every output reg or wire can be read back without special prerequisites, anyone made a thing of it.