`define and +define difference

[mr_vasanth]

Verilog has macro `define as well as provides option to pass +define during compilation.

When to use `define and when to use +define ?
Is there any guideline available ?

 

[ads-ee]

+define allows you to change a define during compilation.

Suppose you have a long timeout in your code and you place an `ifdef SIMULATION around it. You can use +define+SIMULATION to force the code to use the simulation value instead of the synthesis value.