i have designed a voltage reference used in a power IC, just as the picture shows. the 1.25v voltage is generated by bg core, and the 1.5v voltage is a pad connected a 1uF cap on pcb board, so the 1.5v voltage is noiseless. while i have some other voltage reference, such as 0.9v, 0.6v ,etc, that is used for other modules(osc, ldo, charger, etc), and the simulation shows, the 0.9v and 0.6v voltage is noisey for the clock operation, now i want a noiseless 0.9v and 0.6v voltage inside chip, so, what should i do? what methods should i used? i have checked some papers, but no relative ideas. please help me, i want the 0.9v and 0.6v voltage just as noiseless as the 1.5v voltage. thanks.
besides, i also want to decrease the power and ground noise inside chip, what methods should i use?
Due to a (very) high input impedance you can easily LP filter the DC input signal, whereas the low output impedance renders the output node very insensitive against noise influence (by capacitive coupling).
first,must know where noise origin is from? if power or ground is origin, noise of the voltage reference is the same as noise of power or ground. these reference can be used in this ic. if noise origin is from other block, you can use RC filter or buffer