Re: sigma delta ADC
If you use in a sigma-delta modulator a comparator (=1 bit depth), the outputstream delivers only a single bit data. Due to oversampling you have the information for instance 1024 bit lenght. So you have to average the outputstream over time, and this is made during decimation. There are a lot of realization and often you have to take the droop of the sinc (=comb- , average- filter) into design consideration. It's most likely a FIR filter due to the linear phase = constant group delay.
Such filters are easy to realize using a cascade of int and diff!
Besides, the meaning of the word UNDERSAMPLING results from the fact that you reduce the sampling rate as in our example: 1bit@10*Fs to 10 bit@Fs