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decimation filter for sigma delta converter

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svensl

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I have a question about decimation filters. As an example consider a 1st order sinc decimation filter which has one integrator operating at Fs, and a differentiator operating at the decimated rate Fs/R.
Also, assume the output of the sigma delta modulator is a 1 bit binary signal, i.e. 0, 1, 0, 1,1.......

My question is regarding the integrator (accumulator) of the sinc filter. How does one handle saturation of the integrator as it keeps adding ones to its output?

Thanks,
svensl
 

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