Dealing with timing issue in ZYNQ7000

[ABADY1000]

I have a project on ZYNQ7000 chip, I read data from image sensor, apply some processing on the received images, and show it on a display using BT656 protocol.

The problem is that there are many timing issues, and every time I make even a slight modification and regenerate the bit-stream there is a risk new generated bit-stream won't work properly.

I contacted someone to help me fixing timing issues, and he solved it (Vivado shows no timing errors), but after I run the project I found the function of the system is not working properly!

So, what I am asking about is where to go next? What is the method I should follow to fix my problem?

Someone suggested I make post-implementation simulation, the problem here is I am using zynq7000, how would I simulate CPU and RAM(memory)? would using QEMU help me applying post-implementation simulation? or do I need to?

 

[KlausST]

Hi,

I guess you need to set up your timing constraints correctly.
Then your compiler tries to keep within these specifications and reports issues.

Klaus

 

[niciki]

First of all I would suggest to use Synthesized Design Constraints Wizard - to check if unconstrained clocks or unsafe clock's domain crossings exist:

Using the Vivado Timing Constraint Wizard

www.xilinx.com

 

[dpaul]

Make sure your design is constrained properly. Xilinx has tutorials for design constraining. Read them first.
If you if can correctly constrain the design the step of post-implementation simulation can be eliminated. I never perform post-implementation simulation on my designs.