Hi,
We don't know
* what knowledge you currently have
* what you have learned
* what documents you did read
* what videos you watched
Nor do we know what you expect from us.
Give use informations, give us details.
Klaus
Thanks for your reply.Read the memory documentation of the FPGA device you are using, they all have timing diagrams and even code examples of how to infer their RAM/ROMs in VHDL/Verilog.
Or generate a memory IP core and look at the testbench produced by the tools and see how the vendor interfaces to the RAM. You can also run a simulation to see how it works.
If you don't understand how the Fibonacci sequence works then look at the wiki page.
-- Quartus Prime VHDL Template
-- Simple Dual-Port RAM with different read/write addresses but
-- single read/write clock
library ieee;
use ieee.std_logic_1164.all;
entity simple_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port
(
clk : in std_logic;
raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
data : in std_logic_vector((DATA_WIDTH-1) downto 0);
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end simple_dual_port_ram_single_clock;
architecture rtl of simple_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(waddr) <= data;
end if;
-- On a read during a write to the same address, the read will
-- return the OLD data at the address
q <= ram(raddr);
end if;
end process;
end rtl;
Here's a dual port, single clock RAM template.
Code:-- Quartus Prime VHDL Template -- Simple Dual-Port RAM with different read/write addresses but -- single read/write clock library ieee; use ieee.std_logic_1164.all; entity simple_dual_port_ram_single_clock is generic ( DATA_WIDTH : natural := 8; ADDR_WIDTH : natural := 6 ); port ( clk : in std_logic; raddr : in natural range 0 to 2**ADDR_WIDTH - 1; waddr : in natural range 0 to 2**ADDR_WIDTH - 1; data : in std_logic_vector((DATA_WIDTH-1) downto 0); we : in std_logic := '1'; q : out std_logic_vector((DATA_WIDTH -1) downto 0) ); end simple_dual_port_ram_single_clock; architecture rtl of simple_dual_port_ram_single_clock is -- Build a 2-D array type for the RAM subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; -- Declare the RAM signal. signal ram : memory_t; begin process(clk) begin if(rising_edge(clk)) then if(we = '1') then ram(waddr) <= data; end if; -- On a read during a write to the same address, the read will -- return the OLD data at the address q <= ram(raddr); end if; end process; end rtl;
I don't think documentation gonna help me, I'm using pure simulation which is no specific fpga board to handle this code here, thanks.If you are using a Xilinx FPGA, I would recommend to use the Synthesis Guide.
See the topic RAM HDL Coding Guidelines in there. Templates for various RAM types can be found there.
Other FPGA vendors should also have such a document.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 signal F0, F1: integer; begin process (reset, clock) begin if reset = '1' then F0 <= 0; F1 <= 1; elsif rising_edge(clock) then F0 <= F1; F1 <= F0 + F1; end if; end process;
Your question isn't specifically related to RAM, more to implementation of the overall code.The Fibonacci sequence itself can be generated by just two registers and an adder.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 signal F0, F1: integer; begin process (reset, clock) begin if reset = '1' then F0 <= 0; F1 <= 1; elsif rising_edge(clock) then F0 <= F1; F1 <= F0 + F1; end if; end process;
I understand that your exercise problem involves storing the sequence to a RAM. You could read the Fn-1 und Fn-2 from the RAM which might use a FSM, but that's not actually necessary.
write down the data flow..something like
1. address =0, write 0, address++
2. address =1, write 1, address++
now we can start a loop to do the reset of the sequence
3. address = 2, read address-2, read address-1, add the two numbers, write sum to address=2, address++
4. repeat step 3 with address=3,4,5....
Write an FSM that follows that flow. You will probably want to break the steps down further as I've got a lot of steps (clock cycles) compressed together.
I'll test it and tell you, many thanksConsider address as the counter value.
I'm stuck again unfortunately, I can't understand how to assign the counter of the Fibonacci sequences (0 for 0,1 ..... 7 for 13..etc) as an address to the memory, can you explain that to me, because now I want to assign the counter as address then loading theses addresses by the Fibonacci sequences, thank in advance for any help.Consider address as the counter value.
Using the Fibonacci sequence as the address? I suspect that isn't what you are supposed to do. It doesn't make a lot of sense as the address would be way to large in a short number of clock cycles. By the time you've reached the 48th number in the sequence you would end up with an address that is over 2^32 (4Gig).
From you description in your first post you say you are supposed to store the sequence in a RAM. If you make the RAM 64-bits wide you can store quite a few more values. If you store them in sequential locations in the RAM then a counter is what you use, which is what I describe in my previous post with the address++ (increment address, in both C and Verilog).
Also you don't "assign" the counter (or the Fibonacci sequence) to the the address of the RAM. That statement you made makes me think you don't quite grasp that VHDL is not actually the same as your usual programming languages like C++, ADA, etc. Think of VHDL has a way to describe how to hook up chips on a board without drawing the schematic or individual logic gates. So connecting the counter address to the RAM is instantiating a RAM block into your code (or writing a behavior description of the RAM using a template, linked by others) and using port mapping to connect a counter signal to the RAM address port.
Maybe you should look at examples of code that shows how to use RAM e.g. https://vhdlguide.readthedocs.io/en/latest/vhdl/dex.html#random-access-memory-ram which I found after a couple of search attempts (most search results showed how to infer RAM in VHDL with no example of using the RAM, this page has testbenches to run the RAM in a simulation).
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