if you are talking about decreasing the Q factor of an RLC circuit, the resistor is used to dissipate power, thus reducing the Q factor. Q is defined as
Q = 2 • π • (Energy stored / Energy dissipated per cycle).
By introducing a De Q'ing resistor, this resistor dissipates energy.
For a practical RLC parallel circuit Q is given by [1, page 26]
Q_par = 1/R • sqrt(L/C)
and for a series RLC by
Q_ser = ω_0 • L/R = ω_0 • 1/(R • C).
As you can see, the series resistor (in both circuits) leads to a decrase of Q.
As the question is posted in PCB Layout rather than RF or Analog Design section, I fear it's really unclear what "De Q'ing" resistor means for you. Please give a typical example.