dragonfury
Member level 4
Hi Everyone,
I am performing signal integrity simulations for a DDR3 UDIMM with single and dual rank. I would like to understand some of the limits used in the JEDEC standard No 79-3F
1. I would like to know the difference and importance of AC & DC Logic input levels (VIH(AC)& VIH(DC) ) for single-ended signals (Data Signals DQ/DM) in DDR3.
2. For logic High (input) , should the signal level be higher than VIH (AC)min or VIH(DC)min?
3. The slew rate measurement mentioned in the standard presents that it is measured by the linear voltage rise from the VDD/2 level to the highest AC level divided by the time in x-axis. Is it required for the pass/fail criteria of the DDR3 signaling that the VIH(AC)min should be reached or VIH(DC)min is enough?
I am performing signal integrity simulations for a DDR3 UDIMM with single and dual rank. I would like to understand some of the limits used in the JEDEC standard No 79-3F
1. I would like to know the difference and importance of AC & DC Logic input levels (VIH(AC)& VIH(DC) ) for single-ended signals (Data Signals DQ/DM) in DDR3.
2. For logic High (input) , should the signal level be higher than VIH (AC)min or VIH(DC)min?
3. The slew rate measurement mentioned in the standard presents that it is measured by the linear voltage rise from the VDD/2 level to the highest AC level divided by the time in x-axis. Is it required for the pass/fail criteria of the DDR3 signaling that the VIH(AC)min should be reached or VIH(DC)min is enough?