DDR3 PCB design and routing

[metalgarri]

Hi everybody!
I'm doing my thesis on a Texas Instruments dev board with an 8core DSP (tms320c6678) with DDR3, some flash memory etc...
In the next months I have to do the layout for a custom board with this DSP and DDR3 memory. Now, my problem is that I 've never designed and routed a pcb with DDR3 or DDR memory in general.
What are the things that I have to know about this topic to make all the things work?

PS: I'm at the last year of the master, so I have background of analog and digital system level design and integrated circuits, transmission lines and electromagnetic fields in general, work experience in designing prototype with precision analog circuit and mixed signal board with microcontrollers...

thank you!

Carmine

 

[pbernardi]

Well, there are some ways.

One way is really copy the DDR3 wires from an already working design (for example, a reference board), and fix these wires in your design. It is a lazy and somehow idiot-proof way to proceed, and usually provides good results.

If you are going to really route DDR3 connections from zero, you should use a simulation software for help you (Mentor or something like that). DDR3 circuits are very sensitive and needs lots of knowledge in routing - power planes, wiring impedance, avoid grounding cuts, wiring legth, EMC and more, but you seem to know about these topics. If you don´t simulate your circuit, you may need more PCB design waves. You will need a good scope/pointers (at least 2 GHz bandwidth) and a lot of fine adjusts for DDR3 parameters on your DSP FW.

 

[metalgarri]

ok Thank you!
and which software is usually used to do this kind of simulation?

another question: I read that some transmission lines have to be matched to avoid reflection and preserve signal integrity, so what is the tipical technique used? I mean that for example I know that in RF design the impedence of source/load is 50ohms and one can do a trace to match this impedance. In this case is it the same or some termination resistors to the end of the lines are used?

thank you in advance
Carmine

 

[pbernardi]

I know Mentor Hyperlynx, but it is an expensive software.

You should not use resistors to match DDR3 signals. They may disturb the signals, because you have to route the wires to an outside layer to reach the resistors. Keeping the signals in an internal layer is much better, preferentially without vias. The traces must be matched, however, and that is one reason that simulation is helpful.

There are some DDR3 AN that can help you, you should read and understand them:

**broken link removed**
**broken link removed**
https://www.freescale.com/files/32bit/doc/app_note/AN3940.pdf

 

[metalgarri]

ok thank you...
and do you know if a free software exists to do simultion of this things?
For the PCB layout I have to use Altium, do you know if altium offers a tool for simulation or signal integrity test?

 

[pbernardi]

I found a software list here: **broken link removed**

But I do not know any signal integrity simulator for free, as said before this is usually an expensive stuff. You can email the vendor above and aks for quotation, maybe some of them are more accessible.

If you cannot simulate the circuit, you could ask the component supplier (TI) for support. They migth send you a reference gerber file or something like that.

 

[metalgarri]

ok thank you!
Talking more in general, dealing with high speed digital like DDR3 is a matter of experience or it needs more background knowledge? (I mean more than the subjects I wrote before)??

 

[pbernardi]

Well, this question is a bit too generic, don't you think? It is even hard to differentiate experience from knowledge.

 

[marce]

How much PCB design do you know.
Do you know how to do basic layout.
Do you know how to length match signal lines.
Do you understand how to control the impedance of traces.
Are you routing DDR3 Tree or Fly-by architecture and do you understand the implications of both.
Do you understand how to place decoupling caps and how to route them.

 

[metalgarri]

thank you Marce!
that's what I need!
I know all of this things but "tree or fly-by and implications of both" because I have never routed a PCB with DDR3...
thank you for your help!

 

[marce]

Start with AN41-13 from micron, here's a link to there technology page. That's a good start and should answer a few questions and probably create more.
Read that first and have a look around there documentation.
Also have a look at the data sheets and App notes for the processor/dsp you are using there are usually notes for adding DDR memory.

 

[metalgarri]

ehy! it's been a while...
I've read the Micron app note and all the "dependancies" of this app note and now the situation is much much more clear...
Now I have a doubt about the power plane: supposing that I'm using a 6 layers pcb with 3 signal layers and 3 power/ground layer, and I have a 3 voltage levels for power supply: 1v, 1.5v, 1.8v , which voltage do I have to connect to the power plane?
The 1.5v is for the DDR3 memory and DDR3 controller, should I use that for the refence power plane? the 1v is for the core of my dsp and the 1.8v is for I/O...
thank you

 

[pbernardi]

Use the main component voltage.

DDR3 is connected only on 1.5V, so 1.8V and 1.0V are not needed below the memory.
1.0V is the core voltage, and should be the main voltage below the DSP. 1.5V and 1.8V may be connected to this planes as a small island below the IO/DDR pins if needed, or they can even be connected in a secondary power plane. It depends from a lot of factors as layout density, critical signals and ground concept.

So, use 1.5V below DDR3, 1.0V below DSP, with occasional 1.8V/1.5V islands, or use a dual power plane. That's mean the power plane will not be completely solid.

Additional care is needed to avoid plane cuts when routing the signals. A critical signal should not cross from one voltage/GND plane to other.

 

[metalgarri]

ok got it...
and If I use a PCB stack up like that:

signal top
4.5 mils FR4
GND
6.5 mils FR4
PWR
30 mils FR4
signal
5 mils FR4
GND
4.5 milsFR4
signal bottom

the refence of the inner signal layer may be the GND near the bottom, so is it necessary to pay all these attention to the power layer?

 

[pbernardi]

Yes. It is not only the GND that matters, but the current loop as a whole. If the power plane is not close enough, the current path will be bigger. From current point of view, Vcc path is as important as GND path, and should have less impedance as possible (thus, making a plane).