DDR3 memory implementation

[promach]

I am trying to work on DDR3 memory implementation.

1. why there are 2 WRITING and READING states ?
2. what are ACTIVATING and REFRESHING states for ?

 

[dpaul]

I am trying to work on DDR3 memory implementation.

You can only create a simulation modelof the real hardware. In this link you have posted, go to the right hand side and expand the drop-down 'Simulation Models'. The Verilog RTL is available. Time is of essence, save yourself some effort.

 

[promach]

the second set are "Auto Precharge" states ("AP")

once it gets to the end of writing, it does final write + auto-precharge cycle which then lands it cleanly on completion of the write into the precharge state

1) Why A12 has value of "V" ? What does "V" mean ?

2) As for WRITE LEVELING, why "DQS as input, DQ as output" ?

3) Could anyone help with explaining how DQSBUFM.v is used in DDR3 implementation ?

 

[ads-ee]

It says in the file that it is a simulation library file. I'm assuming that means it is a simulation ONLY file for a DQSBUFM primitive in the Lattice part you are using. It most certainly would not be synthesized as such a primitive isn't implemented in the FPGA's fabric.

--- Updated Dec 6, 2020 ---

You are skipping over your reading of the datasheet it plainly states on page 115 Note 6 that V stands for H or L.

You should really read every word from start to finish of the datasheet before attempting to write code for the part.

 

[matrixofdynamism]

It would be great to know why you are trying to create a hardware model of the DDR3 RAM inside FPGA which is what is being implied here actually.

Vendors often provide simulation library that can be used to in simulation of our system.

Please remember that with high speed interfaces, signal integrity issues can often lead to fault behaviour rather than our memory controller having wrong functionality. Finally I would emphasize that it is best to use the memory controller provided by the FPGA vendor i.e use memory controllers that come with Quartus, Libero e.t.c rather than writing your own. This is because it is a very difficult task to write of these memory controllers.

 

[promach]

1. Do I really need tdqs and odt ?
2. Another question is do I need twr for write_AP ?
   
   by the way, I had done an initial code for the DDR3 memory controller in verilog :
   
   https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c

 

[promach]

Please see the latest updated code at https://github.com/promach/DDR

How to write logic for ldqs and udqs ?

 

[student_078]

I remember there is an analog block sitting between digital logic and the DDR pads. Would promach design and simulate that?
I can design the digital part in ASIC and I am looking for open source study materials on the analog part.

 

[promach]

why https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L947 is always 'true' ?

TIME_TRFC + TIME_TRP < MAX_NUM_OF_REFRESH_COMMANDS_POSTPONED

 

[promach]

Sorry line 947 is updated to 952 yesterday. Just check signal 'high_Priority_Refresh_Request'

how shall I understand Figure 4 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh ?

 

[promach]

Could anyone point out if there are issues with this DDR3 initialization sequence ?

Note: The DDR3 RAM memory controller is not working yet so far.

 

[std_match]

Sorry line 947 is updated to 952 yesterday. Just check signal 'high_Priority_Refresh_Request'

how shall I understand Figure 4 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh ?

View attachment 169430

It says that you can skip refresh commands for a while if you make up for it later. The average time between refresh commands must be correct.

 

[promach]

Something is so peculiar with the alternating {3, 0} dq bits
The waveform should not have value of 0 for dq signal.

In other words, why when ldq_w and udq_w are carrying value of 2, 4 or 6, dq carry a value of 0 ?

https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L827-L828

 

[promach]

From the modelsim console log, it seems that the data loopback(readback) works.

However, how to simulate "inout" dqs signals correctly inside modelsim ?
Note: I tried changing 1'b0 to 1'bz , but it does not help.