noisepic
Member level 3
I met a problem in design and buc method for DDR3 signal. In the phase of design we follow matching length but the reality it is not the same as schematic due to:
- Bonding wire length
- manufacturing variations make matching length worse
Do you know design step to win DDR3! any tool support? both in schematic and hardware debug
- Bonding wire length
- manufacturing variations make matching length worse
Do you know design step to win DDR3! any tool support? both in schematic and hardware debug