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DDR3 design bug and how to test

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noisepic

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I met a problem in design and buc method for DDR3 signal. In the phase of design we follow matching length but the reality it is not the same as schematic due to:
- Bonding wire length
- manufacturing variations make matching length worse

Do you know design step to win DDR3! any tool support? both in schematic and hardware debug
 

marce

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A bit more info, what is your allowable skew...
Some IBIS data has bond wire lengths in.
 

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