DDR2 Timing (interconnect) budget calculation

[balamani]

Hi,

I am doing DDR2 Signal Integrity analysis using HyperLynx 8.2.1

To calculate the timing budget , I am in need of step by step procedure for the following measurements.

•ISI (DQ & DQS)
•Crosstalk (DQ & DQS)
•VREF noise
•Path length mismatch
•CIN mismatch

Please explain in detail.

 

[mishrashashi]

Hi Balamani,
for DDR2 timing analysis, please follow datasheets(processor) timing diagram. you have to map timing delay between clock to DQS, then DQS to DQ. CLK to Address and Command.
If you can share part name/ datasheet of processor. I can guide you in timing budget calculation.

For Crosstalk you have to set minimum acceptable voltage level. I usually measure for 50 mV~100 mV for DDR2/3. In worst case I choose 150 mV.

for DDR2 Vref= VDD_DDR/2

 

[balamani]

Hi

Thanks for your reply. Yes I will take care.

Do you have any idea how to to do timing analysis in Hyperlynx tool if I have a PLL in between the Processor and DRAMs?

 

[mishrashashi]

can you share block diagram of DDR section of your design? Please mention how data and control signals are communicating.