[SOLVED] DDR2 SDRAM controller(generated using MIG) for spartan 3A FPGA

[sasi_badveli]

Hello all,
I have few questions regarding CAS Latency. For example,if the DDR2 SDRAM consists of a CAS Latency of 4,and if the DDR2 SDRAM memory controller generated using MIG has a latency of 3? Does the design work together? Any help would be appreciated.

Thanks.

 

[cristianp]

Hello all,
I have few questions regarding CAS Latency. For example,if the DDR2 SDRAM consists of a CAS Latency of 4,and if the DDR2 SDRAM memory controller generated using MIG has a latency of 3? Does the design work together? Any help would be appreciated.

Thanks.

In present, DDR2 CAS Latency is defined for a nominal data rate (DDRAM working data rate). If your design works with a frequency below maximum data rate your design could work properly for a different (lower) latency. The following formula should be respected:

1/Nominal frequency x CAS Latency (4) >= 1/Working frequency x CAS Latency

Example

DDR2-1066 with CL = 4 will work with systems with DDR2-667 with CL = 3

 

[sasi_badveli]

@cristianp: Thank you for the reply.

Can u explain for the following example? If the fpga used is (XC3S200A-4FTG256)spartan 3A and DDR2 SDRAM memory module is MT47H32M8BP-37E? I tried to generate a DDR2 memory controller using MIG tool.But it turns out that the MIG tool does not support latencies of 4 and 5. That is the problem.

 

[cristianp]

From M**broken link removed** (first page) --> CAS Latency = 3 is supported for clock frequency 200MHz (DDR2-400).
So, if 200MHz clock frequency is enough for your design, you can use the generated memory controller that have CL=3

 

[sasi_badveli]

@cristianp:Thanks for the reply.

Can you please explain that in the memory module which i mentioned, in data sheet "-37E" refers to a latency of -4. Also in the micron website,

h**p://www.micron.com/parts/dram/ddr2-sdram/mt47h32m8bp-37e-it?source=ps&q=MT47H32M8BP-37E%20IT,

Can a memory module support different latencies?

 

[cristianp]

CAS Latency is a time. It specify the minimum time between a specific column addressing and data available to output. For synchronous RAM this time is done indirectly by using clock cycles.
Look on the same data sheet on the same page exist Table 1. It mention that this chip support different CAS Latency for different data rates. Note that during DDRAM configuration a CAS Latency of 3 in your case should be mentioned (in configuration word).

 

[sasi_badveli]

Thank you so much for making it clear.