DDR2 controller, MIG, virtex5

Hi there
I using MIG as DDR2 controller in virtex5.
In the MAP stage in Implement Design the following error appears:

MapLib:1114 - IDELAYCTRL symbol "u_mem_controller/u_ddr2_idelay_ctrl/u_idelayctrl" (output signal=u_mem_controller/idelay_ctrl_rdy) has IODELAY_GROUP property "IODELAY_MIG". But the design does not contain DELAY element with the same IODELAY_GROUP name.

I have searched this error in XILINX official website and found the following solution:


UCF Changes :
Add the following IODELAY_GROUP constraints to the UCF file:
INST "*/u_idelayctrl" IODELAY_GROUP=IODELAY_MIG;
INST "*/u_idelay_dqs" IODELAY_GROUP=IODELAY_MIG;
INST "*/u_iodelay_dq_ce" IODELAY_GROUP=IODELAY_MIG;
INST "*/u_idelay_dq" IODELAY_GROUP=IODELAY_MIG


But the problem is I do not have sub modules named as delay_dqs,iodelay_dq_ce and idelay_dq. I do not know what is the solution now :---(