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Hello,
I'm looking into datasheet of DDR2 from Micron https://www.micron.com/parts/dram/ddr2-sdram/mt47h64m16hr-187e. If you see functional diagrams on pages 12-14, there is Column address COL0, COL1 (2 LSBs) going into 4n-prefetch directly. They're not going into column address decoder.
Now my concern is:
This only means we can burst only the "pre-defined" 4n chunk, i.e., from 00,01,10,11 LSBs.
So for example if I needed to burst read 4-data chunks (x4, x8, or x16 bit wide) from current active row, with following column address:
0000 1010 to 0000 1101 (Assuming 8-bit column address for simplicity)
, then its not possible in single burst because the column address decoder is ignoring the 2 LSBs in functional diagram when it is taking the starting column address. 4n-prefetch is automatically assuming the two LSBs to be 00, 01, 10, 11 (in that order).
In other words, the _starting_ column address from 3rd LSB up to MSB is assumed "same" for the burst.
In my example case, the 3rd LSB is changing from 0 to 1 (2 data chunks with 3rd address bit 0, two data chunks with 3rd address bit 1).
In my above example, I'd have to burst read _two_ 4n chunks. One 4n chunk from
0000 1000 to 0000 1011 (ignore first two chunks, 0000 1000 and 0000 1001)
_and_ second 4n chunk from:
0000 1100 to 0000 1111 (ignore last two chunks, 0000 1110 and 0000 1111)
i.e.,
first burst:
0000 1000 (ignore)
0000 1001 (ignore)
0000 1010 (valid)
0000 1011 (valid)
second burst:
0000 1100 (valid)
0000 1101 (valid)
0000 1110 (ignore)
0000 1111 (ignore)
....in order to get data from 0000 1010 to 0000 1101.
So the data chunks/ bursts are 'aligned' already for us. We can only specify the starting column address to be uniform from 3rd LSB upto MSB. And 2 LSBs are automatically assumed to be in order 00, 01, 10, 11.
Is my understanding of the burst alignment issue correct? Please comment.
I'm looking into datasheet of DDR2 from Micron https://www.micron.com/parts/dram/ddr2-sdram/mt47h64m16hr-187e. If you see functional diagrams on pages 12-14, there is Column address COL0, COL1 (2 LSBs) going into 4n-prefetch directly. They're not going into column address decoder.
Now my concern is:
This only means we can burst only the "pre-defined" 4n chunk, i.e., from 00,01,10,11 LSBs.
So for example if I needed to burst read 4-data chunks (x4, x8, or x16 bit wide) from current active row, with following column address:
0000 1010 to 0000 1101 (Assuming 8-bit column address for simplicity)
, then its not possible in single burst because the column address decoder is ignoring the 2 LSBs in functional diagram when it is taking the starting column address. 4n-prefetch is automatically assuming the two LSBs to be 00, 01, 10, 11 (in that order).
In other words, the _starting_ column address from 3rd LSB up to MSB is assumed "same" for the burst.
In my example case, the 3rd LSB is changing from 0 to 1 (2 data chunks with 3rd address bit 0, two data chunks with 3rd address bit 1).
In my above example, I'd have to burst read _two_ 4n chunks. One 4n chunk from
0000 1000 to 0000 1011 (ignore first two chunks, 0000 1000 and 0000 1001)
_and_ second 4n chunk from:
0000 1100 to 0000 1111 (ignore last two chunks, 0000 1110 and 0000 1111)
i.e.,
first burst:
0000 1000 (ignore)
0000 1001 (ignore)
0000 1010 (valid)
0000 1011 (valid)
second burst:
0000 1100 (valid)
0000 1101 (valid)
0000 1110 (ignore)
0000 1111 (ignore)
....in order to get data from 0000 1010 to 0000 1101.
So the data chunks/ bursts are 'aligned' already for us. We can only specify the starting column address to be uniform from 3rd LSB upto MSB. And 2 LSBs are automatically assumed to be in order 00, 01, 10, 11.
Is my understanding of the burst alignment issue correct? Please comment.
