DCM bounds frequency to 150.015MHz

[seeker_123]

In dff code I have used DCM from Language template of xilinx.

------------------------------------------------------------------------------------------------------
module dff_async_reset (data,clk,reset,q);
input data, clk, reset ;
output q;
reg q;

DCM_BASE DCM_BASE_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLKFB(CLK1), // DCM clock feedback
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.RST(0) // DCM asynchronous reset input
);
BUFG BUFG_inst (
.O(CLK1), // Clock buffer output
.I(CLK0) // Clock buffer input
);

always @ ( posedge CLK1 or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

endmodule
-----------------------------------------------------------------------------------------------------------------

and then I have given constraint like
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 3 ns HIGH 50%;
OFFSET = IN 3 ns VALID 3 ns BEFORE "clk" RISING;
OFFSET = OUT 3 ns AFTER "clk";

But timing constraint fails. I have attached timing constraint report image.
Report is saying that best case achievable for clock period is 6.66ns.
Whenever I am using DCM for any design it says that best case achievable for clock period is 6.66ns.


Why it is happening ? Is it case that DCM can achieve maximum of 150 mhz?



I am working on vertex5. xilinx 13.2

Please guide me on this.

Thank you................

 

[barry]

You can't have a clock with a period of 3ns and an offset of 3ns. What you are saying is that you want a setup/hold time equal to the clock period-->physically impossible. Maybe what you want is a multi-cycle constraint? What is it you are REALLY trying to specify here?

 

[seeker_123]

thanks ....

sorry thats my mistake.....
now i have given like

#Created by Constraints Editor (xc5vlx155-ff1153-3) - 2013/04/08
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 5 ns HIGH 50%;
OFFSET = IN 3 ns VALID 5 ns BEFORE "clk" RISING;
OFFSET = OUT 4 ns AFTER "clk";


now input offset constraint and output offset constraint is meeting but clock period constraint is not meeting.


now what i am asking is
whenever i am using DCM then clock period is 6.66ns means freq is limiting to 150.015 Mhz
i am expecting more frequency as it is only single flip flop ...............

so my question is whether with DCM we are getting maximum freq of 150 Mhz.?

 

[barry]

Your constraints are still no good. If you are going to use the VALID parameter, I don't think you want/need the OFFSET=OUT constraint. The VALID constraint intrinsically sets the hold requirement, which is also what the OUT constraint does. Get rid of the VALID constraint.

Further, you've got a 3 ns setup time and a 4 ns hold time constraint. That's 7 ns for a 5 ns clock. Does anything seem wrong to you?

 

[seeker_123]

thanks again ....
now i have given constraint

NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 5.5 ns HIGH 50%;
OFFSET = IN 2.1 ns VALID 5.5 ns BEFORE "clk" RISING;
OFFSET = OUT 3.1 ns AFTER "clk";

now in this case offset in and offset out is meeting but with clock period constraint same problem persist...

now as u suggest there is no requirement of offset out
i have removed both offset in and offset out because i want to know what is clock frequency achieved with DCM Now i am not focusing on offset in and offset out
now my UCF file is
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 5.5 ns HIGH 50%;

so result for this is
1 constraint not met.
Design statistics:
Minimum period: 6.666ns{1} (Maximum frequency: 150.015MHz)
I have attached constraint table


Thanks...

 

[barry]

Ok, so your design doesn't meet timing. Now you need to figure out why. If you look at your timing report it should show you worst case paths.

What is your required output frequency from your dcm? Maybe that's limiting the input frequency.

 

[seeker_123]

Thanks barry for your continuous attention

Now i have checked timing report and it shows me which is worst case path which is limiting input frequency
There are two timing error period constraint
Below are that two paths from timing report

Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 5.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -1.166ns (period - min period limit)
Period: 5.500ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpc)
Physical resource: DCM_BASE_inst/CLKIN
Logical resource: DCM_BASE_inst/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: clk_IBUFG
--------------------------------------------------------------------------------
Slack: -1.166ns (period - min period limit)
Period: 5.500ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpco)
Physical resource: DCM_BASE_inst/CLK0
Logical resource: DCM_BASE_inst/CLK0
Location pin: DCM_ADV_X0Y0.CLK0
Clock network: CLK0
--------------------------------------------------------------------------------


so here it is saying that minimum period limit for dcm is 6.66ns

thats what i am asking from start is whether with dcm we will get max freq is 150.01 mhz(6.66ns)...?


and as you have ask
---------------------------------------------------------------------------------------------------
What is your required output frequency from your dcm? Maybe that's limiting the input frequency.
---------------------------------------------------------------------------------------------------
I just want to check max freq achieved with DCM so i just give period below 6.66ns to verify
but i couldn't get why min period limit for DCM is 6.66ns

so please help me in that ....



thanks again

 

[barry]

When you create a DCM, you specify input and output frequency (or multiplier). What parameters have you used?

 

[seeker_123]

When you create a DCM, you specify input and output frequency (or multiplier). What parameters have you used?

I have created DCM from language template having all default parameter.
I have given my code along with DCM in my first post


here is the code for dcm instantiation from language template

DCM_BASE #(
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_BASE_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.RST(RST) // DCM asynchronous reset input
);


but as i don't require others i have removed other values.

thanks

 

[barry]

That's very difficult to translate. It LOOKS like you've specified an input clock of 10nS (100MHz) and a multiply of 4==> CLKFX=400MHz. Well, maybe your device can't run as high 400MHz because you've selected LOW FREQUENCY mode. Again, what were your specified input/output frequencies?

 

[mrflibble]

I have formulated a brilliant backup plan of what to do when you don't understand DCMs and/or don't quite have the time to read the datasheet for sneaky details.

The Plan [tm]: use core generator to pointy-clicky your DCM core. Then when you get it working you can look at what DCMs were generated, how the buffers and clock feedback is connected, etc. Core generator does nothing more than instantiate primitives just like you are using, only then with correct values. So then you use this know-to-work instantiation as inspiration to make your own. Been there, done that.

 

[barry]

I have formulated a brilliant backup plan of what to do when you don't understand DCMs and/or don't quite have the time to read the datasheet for sneaky details.

The Plan [tm]: use core generator to pointy-clicky your DCM core. Then when you get it working you can look at what DCMs were generated, how the buffers and clock feedback is connected, etc. Core generator does nothing more than instantiate primitives just like you are using, only then with correct values. So then you use this know-to-work instantiation as inspiration to make your own. Been there, done that.

I was assuming that was actually what he DID do. Maybe not. If OP tried to create the DCM without using core generator, then I wish him well and I'm outta here. There does seem to be a lot of unnecessary flailing about.

- - - Updated - - -

I have formulated a brilliant backup plan of what to do when you don't understand DCMs and/or don't quite have the time to read the datasheet for sneaky details.

The Plan [tm]: use core generator to pointy-clicky your DCM core. Then when you get it working you can look at what DCMs were generated, how the buffers and clock feedback is connected, etc. Core generator does nothing more than instantiate primitives just like you are using, only then with correct values. So then you use this know-to-work instantiation as inspiration to make your own. Been there, done that.

I was assuming that was actually what he DID do. Maybe not. If OP tried to create the DCM without using core generator, then I wish him well and I'm outta here. There does seem to be a lot of unnecessary flailing about.

 

[mrflibble]

I was assuming that was actually what he DID do. Maybe not. If OP tried to create the DCM without using core generator, then I wish him well and I'm outta here. There does seem to be a lot of unnecessary flailing about.

Well, he did say:

I have created DCM from language template having all default parameter.
...
but as i don't require others i have removed other values.

So I think he's doing precisely that ... doing an instantiation from the language templates, removing parameters that he doesn't like and then hope for the best. You can use the language template just fine, but you really should be reading the datasheet in that case because there are some details to be taken care of. If that's too much work, use core generator.

For best results: use core generator, see that it now suddenly works (yay!), THEN read the vhdl or verilog code that core generator spat out, and THEN read the datasheet to see what it all means.