TonyLS
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I have one small stand alone module that is taking a long time to map. It's been stuck on Pass 1 Mapping for a very long time.
This module was re-coded but none of the verilog experts in the group can pin point the problem. It elaborates fine.
Is there a way of having dc_compiler tell me what it's having a hard time with in the module?
Any info pertaining to this issue is appreciated
Thanks
This module was re-coded but none of the verilog experts in the group can pin point the problem. It elaborates fine.
Is there a way of having dc_compiler tell me what it's having a hard time with in the module?
Any info pertaining to this issue is appreciated
Thanks