dc Vs primetime: reasonable slack or not?

[kaisopos]

hi all,

I get a significantly different slack in dc and primetime. Since I am a newbie, I am not sure if this is reasonable or I did something wrong.

the details:
I synthesized my design in dc and I fed the synthesized netlist to primetime (with exactly the same constraints file and the same .lib file). So, dc could meet timing for frequencies up to 500 MHz (2ns clock): for 500MHz I got 0 slack, while for 550MHz I got a -0.11ns slack).
However, primetime indicates that for a 2ns clock I have a 0.34ns slack, which implies that I could run my design at 1/(2-0.34)ns = 600MHz. I am aware that dc does very basic timing analysis, while primetime is pretty accurate, but does this account for such a huge (17%) slack diff, implying that I could run at 100MHz more? What do you think? Did I mess up something or is this reasonable?

thanks a lot!
-Kostas

 

[kaisopos]

hi again,

Are the info I provided incomplete? I am just looking for a "yes, its reasonable" or "no, it seems that you did something wrong". Can someone that has done something similar before just express his opinion?

thanks!
-Kostas

 

[johanlo]

Hi,

DC has the capability to do a virutal layout, and with hints about the layout and correct constraints DC should be within 5% from e.g. IC Compiler.

To get accurate reports from Primetime you need to give the tool information like RC data from StarRC and a netlist with clock tree inserted. If this is not given, Primetime will use a wireload model for calculating the net-delay. Wireload models are usually very optimistic.

So you have not done anything wrong, since Primetime needs more data to be accurate.

 

[cie40]

Hi,

In case of PrimeTime,

set auto_wire_load_selection "false"

Thanks.

 

[kaisopos]

thanks people!

 

[viju]

What is finally concluded? This is a really a interesting topic for me. Please comment.

CIE40 ;
Will setting set auto_wire_load_selection "false" will solve this problem/

Thanks