[SOLVED] DC-topo Synthesis Question: How to force buffers to be inserted in lower hierarchy?

[chitattam]

I am working on a design which has hierarchy structure like this:

.top_level_hier
......|
......- wrapper_hier
............|
............- lower_hier
..................|
..................- even_lower_hier

I am running DC-topo synthesis. Due to some issues caused by voltage area coverage in later stages in ICC, I need to prevent buffers/inverters being inserted in "top_level_hier" and "wrapper_hier" hierarchies in DC-topo. These 2 hierarchies should not contain any standard cells for some methodology reasons in our project.

What command(s) should I use to instruct the tool not to insert buffers/inverters in top_level_hier and wrapper_hier hierarchies but to insert in the lower hierarchies?

Thanks in advance!

 

[chitattam]

Never mind. Tried 'set_dont_touch' and it seems working. Thanks!