DC synthesis result violates design rules constraint

[DSD]

Hi, all

If DC synthesis result violates design rules constraint(max_capacitance, max_fanout) but meets timing requirtment, how does this affect the later design process and the chip's function and timing?

How to set the appropriate design rules constraint on a given design?

Thanks & best regards

 

[linuxluo]

hi,
in DC, the top priority is design rule , then timing. so find out why these violation is not be fixed.
if it's high fanout net , it can be set ideal and let it to BE handle it.

 

[shiv_emf]

If design rules r violating then u may face prob at fab! he may not support ur DRC >.....

 

[firewire2035]

most design rule violations can be fixed in the backend. but your violations can be a indication with the quality of your synthesis, such as dont_touch_network is creeping into your datapaths.

 

[lakshman.ar]

have to specified the DRC values too less ... ???
cos there will be default values for the DRC specified in the .lib file, Incase if u had specified a lesser ( more constraining value) value then the tool tries to the meet tht value, ....

so u mite end getting violations which may have caused bcos of ur wrong constraints . Please specify a correct of default value for hte DRC and then chk the timing !!!

the DRC take more priority than the optimization constraints.

The timing tool will not violate the DRC to meet the Optimization constrains ( inout delay, output delay, create clk, clk uncertainty, clk latency ... etc ). So its the quality of the synthesis thtz being perfomed.

hw can ur design meet the timing if ur DRC is not met ..

as said above ... transtion/ max fanout violations can be fixed at the backend level too !!!!