dc offset of a PD cell. need help!!!

[needforspeed]

Hi guys,
A PD(proportional plus derivative) cell was designed and fabricated, as shown in the following figure.
Ideally, we have Vo[n]=-((C1+C2)/C3)Vi[n]+(C1/C3)Vi[n-1], which is what we get in simulation. However, measurement result is Vo[n]=-((C1+C2)/C3)Vi[n]+(C1/C3)Vi[n-1]+Con. Con is a constant, about -250mV. This DC offset is not acceptable in our system.

I have no idea why this DC offset happen after fabrication, and how to minimize it. Do you have any idea about it? Thanks in advance.

 

[sam185]

You need to put resistance on both inv/non-inv terminal to cancel the offset.

 

[needforspeed]

You need to put resistance on both inv/non-inv terminal to cancel the offset.

we have used auto-zeroing in the circuit, so offset of opamp should be cancelled.
And I don't understand how resistance can cancel offset. could you elaborate it?

 

[sam185]

This happen due to unequal voltage difference on the i/p.

---------- Post added at 06:31 ---------- Previous post was at 06:22 ----------

generally opams are made up of pair of bjts/fets hence there bias char are some time different, so that create a difference in o/p and results in offsets i.e false o/p voltage.