#### jessy_kjl

##### Newbie level 2

entity DU is

Port ( gcd_inA, gcd_inB : in STD_LOGIC_VECTOR (3 downto 0);

selP0 : in STD_LOGIC;

selQ0 : in STD_LOGIC;

ldP : in STD_LOGIC;

ldQ : in STD_LOGIC;

ldG : in STD_LOGIC;

reset : in STD_LOGIC;

clrG : in STD_LOGIC;

opcode : in STD_LOGIC_VECTOR (1 downto 0);

clk : in STD_LOGIC;

gcd_out : out STD_LOGIC_VECTOR (3 downto 0);

Eq : out STD_LOGIC;

Lt : out STD_LOGIC;

data_outP, data_outQ, alu_out : buffer STD_LOGIC_VECTOR (3 downto 0));

end DU;

architecture Behavioral of DU is

begin

regP: process (ldP,selP0,clk,gcd_inA)

begin

if reset='1' then

data_outP <= "0000";

elsif clk'event and clk='1' then

if ldP ='1' then

if selP0 = '1' then

data_outP <= gcd_inA;

end if;

end if;

end if;

end process regP;

regQ: process (ldQ,selQ0,clk,gcd_inB)

begin

if reset='1' then

data_outQ <= "0000";

elsif clk'event and clk='1' then

if ldQ='1' then

if selQ0 = '1' then

data_outQ <= gcd_inB;

end if;

end if;

end if;

end process regQ;

regG: process (ldG,clrG,clk)

begin

if clrG='1' then

gcd_out <= "0000";

elsif clk'event and clk='1' then

if ldG='1' then

gcd_out <= data_outP;

end if;

end if;

end process regG;

ALU_module: process(data_outP,data_outQ,opcode)

begin

case opcode is

when "00" =>

alu_out <= data_outQ - data_outP;

when "01" =>

alu_out <= data_outQ - data_outQ;

when "10" =>

alu_out <= data_outP - data_outP;

when others =>

alu_out <= data_outP - data_outQ;

end case;

end process ALU_module;

--comparator;

Eq <= '1' when data_outP = data_outQ else '0' ;

Lt <= '1' when data_outP < data_outQ else '0' ;

end Behavioral;

in the rtl schematic, the buffers appear as output. why is this so?

thanks in advance!