well,
to do a synthesis, you need the RTL code and the liberty file which define the std cells/pad/memories/custom macros, to generate a netlist in verilog usually.
to insert the DFT (as scan chain), some synthesis tool could do it or used a dedicated tool, normaly the liberty with RTL or netlist is enough.
to do the pattern generation, the netlist and the std cells/pad/memories/custom macro model faults is needed to generate the scan patterns (for stuck-iddq-bridge-transition-small delay-UDFM).