Data setup time and Data Hold Time

[Augustin_gandhi]

Hi Everybody,

Explain me about Data Setup time, Data Hold Time, Address Setup time and Address Hold time. And also tell me how these terms affects the System Clock Frequency.How to calculate the Maximum frequency.

Thanks & Regards,
Augustin.A

 

[VVV]

Every type of sequential logic requires that an input signal be present before the active clock of the edge. This is the set-up time.
There is also a requirement for the input signal to stay for a while after the active edge of the clock. This is known as the hold time.

When these timing parameters refer to certain signals, say the data or address lines, then they are called data and address set-up and hold times respectively. That is to differentiate between them, since they may have different values.

As you can see, since you need to have your input present for a certain time before and after the clock edge, it follows that the clock can have a maximum frequency that still allows the set-up and hold times to be met. That means that the period of the clock cannot be shorter than the sum of the set-up and hold time.

Tclkmin=tsetup+thold or fclkmax=1/(tsetup+thold)

That is the absolute maximum clock frequency you can even consider, based on the maximum values for set-up and hold times.
In practice it will be lower, since there may be other propagation times involved (such as through additonal gates), capacitive loading (which slows down the signals, making them reach the threshold later, effectively stretching the set-up and hold times), etc.

 

[Augustin_gandhi]

Hi

Thanks a lot for your Valuable answers.

But somebody says that we have to consider only the setup time to calculate the maximum frequency. Is it correct? orIn What Assumption they are saying like this??

Thanks & Regards,

Augustin.A

 

[VVV]

Quite frankly I don't know why somebody would say that.
Both parameters have to be met at the same time.
Do you have anything more specific than just the things you mentioned?