Data Passing between Multi Phase clock

[uditkumar1983]

Hi Friends,
I wants to know if two clock having phase difference(Freq. is same) then how to pass data between these two clock ?
as I am thinking we can use two method
(1) By using asy. FIFO. or
(2) By inserting buffer in clock domain such that both edges will come at same time to both side.

Please Give me your suggestion ? which techinque will be better and why ? or if u know any other technique please tell me ..
Regards

 

[vlsi_freak]

You can use two FF based syncronization.

If you trying to sync data, you can go for FIFO.

Hope it helps. If still in doubt let me know.

Thanks

 

[master_picengineer]

Hi,
You can use synchronizer.

 

[avimit]

I would go for
By using asy. FIFO.
Kr,
Avi
http://www.vlsiip.com

 

[master_picengineer]

Interresting, I'm investigating this issue avimit. The only thing that bugged me is the implementation of such a mixed (synchronous/asynchronous) design.
Flow and tools are for me so far not clear. Could you please give an breef explanation.

Thanks.
Regards,
Master_PicEngineer.

 

[sanjay11]

1. If the clocks are of same frequncy but from different sources, then you need to check if there is any ppm diff. between the two clocks. If there is any diff. then even using an asynchronous fifo won't help. As ther fifo may go empty/full after some time. You need to design special FIFO for it.
3. If there is no ppm difference, then using an asynchronous FIFO is a good option.
4. Usually flop based sync. techniques are not used for data bus as it every bit of data may be in diff. phase.

Regards,
Sanjay

 

[shockie]

Is there any good solution for these multi-clock domain issues.