DAC using MiMCap, How to reduce parasitic capacitence

[a991852]

Hi All,

I'm currently drawing a 12-bit DAC in TSMC 180nm Technology, and I'm using a 1f, 2f, 4f approach where the capacitances are doubled for every bit.

This is my layout



And this is one of the corners



However, I'm getting this problem with large parasitic capacitances that are a few times greater than the unit capacitance, and it causes effective number of bits (ENOB) to 6 or 7. Since with all the bits set as 1, the output value is about 950mV, compared to 1V.

Is there a way to reduce parasitic capacitances?

Thanks all

 

[tgootee]

I am not familiar with what you are doing. But, in general: Remove any ground plane? Increase separation between conductors? Make conductors shorter/narrower?

Maybe the best way would be to simply use the parasitics as part of the circuit (i.e. take them into account, in the design).

 

[keith1200rs]

It looks like your unit capacitor is far too small.

Keith

 

[a991852]

Thank you guys for your replys!

To tgootee, what I am doing is the a common-centroid layout, the unit capacitance are layed-out with a specific pattern. The reason why I cannot use parasitics as a part of the circuit is that the largest bit, for example 12, has at least 50% of the parasitic proportion. The parasitic capacitance are not in proportion with each bit.

To keith1200rs, I'm using the smallest unit capacitor as I can, because the size of the DAC is 700um x 700um, which is as big as the other circuit combined. The area that I was allowed for tape-out for my circuit is just 1.5mm x 1.5mm. I was also thinking increasing the size of the DAC, but this would make the circuit too big. Is there any other way?

Thanks again

 

[keith1200rs]

How many capacitors do you have there? Is that the closest capacitor spacing you are allowed? You probably need to try to make sure that the parasitics are identical for each size. This could involve extra connections even though you don't need them otherwise, just to balance the parasitic effect. Is it a sensible solution to your DAC problem?

Keith

 

[a991852]

Thanks for your reply!

To Keith1200rs,

There are
1 (bit 1)
2 (bit 2)
4 (bit 3)
8 (bit 4)
16 (bit 5)
32 (bit 6)
64 (bit 7)
128 (bit 8)
256 (bit 9)
512 (bit 10)
1024 (bit 11)
2048 (bit 12)

Capacitors.

I think I can try larger capacitance are try to put extra metals (connections) to balance the parasitic. The biggest issue is that the parasitic capacitance on the largest capacitor array is greater than the unit capacitance. I will try to increase capacitance and see the results.

Thank you for your recommendation!

 

[keith1200rs]

Could you show the whole layout (upload the GDSII file)?

Keith

 

[a991852]

Hi, thanks for your reply!

This is the GDS file, technology is TSMC 180nm

View attachment DAC2.rar

 

[Yarrow]

Hi, I am currently working on an 12bit SAR ADC which includes a SC DAC. Today I started analyzing the effect of top plate capacitance as well. I loose about 20 % (estimated based on the PDK values) of the reference voltage at the output of the DAC due to the capacitive voltage divider effect. Therefore I also wonder how to counter/reduce this effect, without reducing the parasitic capacitance or increasing the reference voltage.

 

[xingkongwu]

maybe you can use two sub_DAC to get a DAC of 12b which can reduce you area

 

[a991852]

Thanks for your reply!

To Xingkongwu, can you explain to me what is a sub_DAC? Or any information I might be able to find? I tried to search for sub DAC on google, but it didn't say much.

 

[xingkongwu]

hi ,i mean you can use two 6b_DACs to achieve a 12b DAC

 

[dick_freebird]

You can miminize parasitics, or you can minimize their
consequences (such as driving the bottom plate with
a stiff enough amplifier that the parasitic charge is
just "eaten").

But you mention these "large parasitics" without any
info on where they come from, what they're doing to
the circuit.

Driving a large cap probably means wanting a scaled
driver that's capable of the job (or, segment driver+cap
and instantiate 2^{1,2,4,8,...} if you're going be making
a binary weighted design (as opposed to R-2R / 2C-C).