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DAC sin wave Rom calculations LUT

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PeterUK2009

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Hi!

I'm getting stock on creating a LUT for waveform in this case sin wave. I am posting here to get other people opinion and perhaps some help on getting the values.

I have doing some code using a sin function, but I am at trying to do it with a ROM table.

I have manage to get in excel values from angle to normalize value to -1 to 1 but what about when I want to refer it to let say 2.5V.

Let amuse we have 10 bits and we have 100 Mhz clock.

Could you please help with your opinion, formula, example (ideally VHDL)?

Thanks
 

BradtheRad

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what about when I want to refer it to let say 2.5V.
Do you mean that your microcontroller will send High/Low pulses? Out 10 bit wires?

Then 2.5V is a zero crossing.
0V is a trough.
And 5V is a peak.

If each bit wire is Hi or Lo, then you can obtain 0 to 5V by sending an unsigned value between 0 and (2^10)-1 to the DAC.
 

permute

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For any DAC system, you would need to know the transfer function of the normalized digital value to the actual output voltages. For most DAC's, this would be based on "Vref" or "Iref" and more information would be in the datasheet of the DAC. "multiplying" DACs have a reference that is intended to be adjusted. This can be used to perform signal multiplication, or to preserve dynamic range when changing volume. You also should look at any filtering applied if you are using the DAC for signal content near the top of its sampling rate range.
 

Aser

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PeterUK2009

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Thanks permute for your input.

Could you please elaborate more?

Let talk about a particular example like DAC900 from TI I am attaching a picture from the datasheet showing their typical circuit. The complete datasheet could be found here!

dac900.png

The Vref I though it has to be with the output value. So if we supply 3 V the max value should be 3 at 1111111111 address. Right?

- - - Updated - - -

Here you are examples http://kanyevsky.kpi.ua/Studentam/labexercise 1.pdf.
The outputted data is for the DAC input, which output voltage arrangement is out of the synthesable VHDL scope.
Thanks Aser for you lab file. I have read it and I still not sure how to extract what I need to my table creation.

I have create a table on excel using sin fuc. so I start at 0 to have sin=0 as it should and I find the it complete cycle at 360. the value range from 0 to 1. all sound easy now.

I know my DAC (in this example) is running at 100 MHz so that is 100M sample per sec. (the faster signal to be created would be 50M as we will have two sample per half cycle)

But let say we want to create a 1 second period signal. that mean we will need 100M values (let assume we will storage all the values in the fpga ran) from range 0000000000 to 1111111111

(I am also accounting the values will go from 0V to 3V like the signal have a DC value which should be like 1.5V, right?)

to make all easier if I say I want to create a SIN output to 100Hz that means 1M sample per cycle.

according to the file you sent would this be the equation S = sin (2*PI*i/M) give some weird values like 500 half cycle to -2.44921270764475E-016

I know how should look like just I don't know how to calculate it, for this example I should see at 0 value equal to 1000000000 at 750 value should be 0000000000

at 250 value I know it should be 1111111111 and 1 M should be 01000000000, right? I don't know what equation should I use to calculate the value in between?

Please feel free to help!
 

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