DAC error in sigma delta modulators

[pankaj jha]

hello everyone!!

I am reading the book "CMOS cascade sigma delta modulators for sensors and telecom - Error analysis and practical design".

In the first chapter, while discussing about the DAC errors in ∑Δ modulators it says--



"" for a 4-bit sigma delta Modulator with 16-bit linearity, the required matching of the unit elements in the DAC should be better than 0.01% (13 bits). Unfortunately, component matching that can be achieved in present-day standard CMOS processes is in the range of 0.1% (10 bits), so that the required accuracy in the unit elements could only be obtained through the parallel connection of many (over 64) large components. ""

Can anyone elaborate on this? My question is how a matching of 0.01% corresponds to 13 bits. Is there any formula which connects the two?

 

[erikl]

... how a matching of 0.01% corresponds to 13 bits. Is there any formula which connects the two?

matching_requirement and converter_accuracy are inversely proportional to each other:

matching_requirement = 1/(2^13) = 1/8192 = 0.000122 ≈ 0.01%

 

[pankaj jha]

matching_requirement and converter_accuracy are inversely proportional to each other:

matching_requirement = 1/(2^13) = 1/8192 = 0.000122 ≈ 0.01%

Thanks for ur prompt reply!!!!
Thanks again for the relation between matching_requirement and converter_accuracy.

moreover i would like to ask another question. how do we fix '13 bits' for 4bit ΣΔADC of 16bit linearity, why not 12 bits or 14 bits?