For a D Flipflop with Enable how the else part can be coded? Generally the rtl of a D-Flipflop with enable are as below and it does not show an else part. How to take care then to avoid latch generation ?
According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?
Will there be edge sensitive enable flipflops in library to realize the following edge sensitive RTL for D Flipflop ?
Code:
always @ (posedge clk or negedge rest or posedge enable)
if (~reset)
Q<= 1'b0;
else if (enable)
Q<= d;
If intended as DFF description, it's erroneous. According to Verilog rules, enable will be implemented as second asynchronous signal. Because the design is missing code to be executed on the clk edge, no DFF will be implemented, only a latch. To generate a DFF with enable input, "posedge enable" must not appear in the event list, the correct code is in post #1 and #2.
Is my following reasoning correct to correctly and completely answer my first question in post #1?
According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?
I am getting puzzled. So can you please answer the below question which was asked in post # 6?
Is my following reasoning correct to correctly and completely answer my first question in post #1?
According to Verilog LRM for the procedural assignment Q<= d here, the Q will have to hold the earlier value when Enable=0. So in this case the synthesis tool will try to generate a flipflop as the flipflop will hold the previous value when Enable =0 and also the synthesis tool will not synthesize latch as the always block is edge sensitive and not level sensitive Is this that is the reason for latch not being generated out of this code?
I think, the conclusion is incorrect or at least misleading in so far that a flipflop won't be generated only in this case, but in any case with or without enable, with or without reset. But also in this case.
The other part has been answered before in post #2 and #3: An edge sensitive always block always generates a flipflop and never a latch.