jeevaaraam
Member level 2
I have used following part in one of my design.
Part #: 74HCT74PW
Function: D-type ?ip-?op
Description: Dual D-type ?ip-?op with set and reset; positive-edge trigger;
TTL-enabled
Refer attached circuit diagram.
The Net ‘CNT_RST’ is connected to GPO of microcontroller to clear the flip-flop.
The Net ‘RESET_CNT’ is connected to GPI of microcontroller to get the status.
Clarification required:
My expected output will be HIGH, only when the SD=HIGH, RD=HIGH and also CP is in
positive rising edge. But, I’m getting output pin-5 (1Q) as HIGH, when the CP is
in low state (While power ON). Whether my understanding is correct or not.
On power up, what is the STATE of pin Q (When CP = 0)?
Part #: 74HCT74PW
Function: D-type ?ip-?op
Description: Dual D-type ?ip-?op with set and reset; positive-edge trigger;
TTL-enabled
Refer attached circuit diagram.
The Net ‘CNT_RST’ is connected to GPO of microcontroller to clear the flip-flop.
The Net ‘RESET_CNT’ is connected to GPI of microcontroller to get the status.
Clarification required:
My expected output will be HIGH, only when the SD=HIGH, RD=HIGH and also CP is in
positive rising edge. But, I’m getting output pin-5 (1Q) as HIGH, when the CP is
in low state (While power ON). Whether my understanding is correct or not.
On power up, what is the STATE of pin Q (When CP = 0)?