Short answer: Indeterminate.
You should assert your reset signal after power-up if you want to be sure that the Q output is low.
Just useless.I had added pull down resistor (1k) at the output pin Q (pin 5) to define the state of the pin.
I had added pull down resistor (1k) at the output pin Q (pin 5) to define the state of the pin. I have observed that the output is always LOW (0V), even the CP is in positive rising edge. The output should go to logic HIGH, when CP is in positive rising edge.
That is a naive reading of the data sheet. It says nothing of the power-up state.
Yes, You are correct, the default state is not mentioned in the datasheet. The default state had got from manufacturer support team before designing. The simulation results show as LOW state (Again, It is also based on the model, may not give the actual IC characteristics)
You might try putting a small (100pF) cap on the reset input to hold it low a bit longer on power up so it will force a reset.
As other option,
I have changed the expected output as LOW, when event is occurred (CP is in rising edge). Then, the state change will happen from HIGH (Default on POWER ON) to LOW.
Your second option solves nothing. You can put all the pulses you want on the D input and it's not going to change anything. You could put the pulse on the SET or RESET input.
You need to understand two things:
1) The flip flop will power up in an indeterminate state.
2) If you don't actively set it or reset it, you WILL NEVER KNOW what state it is in.
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