D flip flop cell that change state on clock pulse

[gGololicic]

In my exam I had to design a logical circuit with D flip flop cell which responds to a clock signal during the low-to-high transition of a clock pulse, but given D flip flop responded to a high clock pulse. So the absolute right way of doing this was with following design:



But since I was not really 100% sure I remembered that design corectly I wrote my own. This is what I designed and I want to know if it could work (in theory and in reality) ?

 

[crutschow]

In theory, with ideal devices, your circuit wouldn't do anything since the inputs to the AND gate are never high simultaneously.

In reality, your circuit will output a narrow pulse on the low-to high transition of the input with width approximately equal to the propagation delay of the inverter. Is that what you intended?

 

[gGololicic]

Is that signal width long enough to change the state of flip flop?
Or even better asked could this two logical circurit works the same if we looked at the as black boxes and just watch the input and output?

 

[crutschow]

Is that signal width long enough to change the state of flip flop?
Or even better asked could this two logical circurit works the same if we looked at the as black boxes and just watch the input and output?

Whether is works or not depends upon the actual pulse width and if that width if long enough to clock the particular flip-flop.

Even if it works, your circuit does not provide an inversion of the clock signal, which the correct circuit does. All yours does is change a low-high clock transition to a low-high-low pulse. Thus the Flip-Flip is still triggering on the low-high transition, not the high-low transition as the inverted clock provides.