Cyclone IV, Nios II, EPCS64

[FrenchRiviera]

Hi all,

I am building a custom system, using an FPGA board with a Nios II processor. I'm using Quartus 15.0 and DE0 NanoBoard( Cyclone IV as FPGA)
My application contains:

1. Clock Source
2. Nios II Processor
3. System ID
4. JTAG UART
5. EPCS Serial Flash Controller
6. PIO
7. SDRAM Controller

The SDRAM aims is to store instructions and data for NIOS application. The EPCS64 flash aims is to store the FPGA configuration data and the nios firmware.
So, the system can boot from flash for both hardware and software.

Now, I trying to write/read into/from the flash device. Unfortunately, what I write and read is not similar.

Below is the code for both writing and reading operations:

int Write_flash( alt_flash_fd* fd, float *Ks_para,int test_offset)
{
  int i;
  int ret_code = 0;

  alt_u8 *ptr_ks=(alt_u8*) Ks_para;

  int test_length = sizeof(Ks_para);

  // before writing in a sector, we should erase it before
  ret_code=alt_erase_flash_block(fd, test_offset,regions->block_size);
  if(!ret_code){

    for(i=0;i<test_length;i++){
        printf( "data_written[%d]= 0x%08x\n\r",i,ptr_ks[i]);
    }

    //ret_code = alt_epcq_controller_write_block(fd, test_offset, test_offset,ptr_ks, test_length);
    ret_code=alt_write_flash_block(fd,test_offset,test_offset,ptr_ks,test_length);
  }
  if (ret_code)
  {
      printf( "\nERROR: function alt_write_flash failed. ret_code %d\n",ret_code);
      return ret_code;
  }
  return ret_code;

}

float Read_flash( alt_flash_fd* fd,int test_offset)
{
  int test_length = 4;
  alt_u8 data_read[test_length];
  int i=0;
  union conv2float read_flash;
  float Ks_para=0.0;
  int ret_code = 0;

    if (!ret_code)
    {
      //ret_code = alt_epcq_controller_read(fd, test_offset, data_read, test_length);
      ret_code=alt_read_flash(fd, test_offset, data_read, test_length);

      if(!ret_code)
      {
        for(i=0;i<4;i++){
          read_flash.V_In[i]=data_read[i];
            printf( "Flash+%d= 0x%08x\n\r",i,read_flash.V_In[i]);

        }

          Ks_para=(float)read_flash.V_Fl;
      
      }
    }

    alt_flash_close_dev(fd);
    if (ret_code)
    {
      printf( "\nERROR: function READ failed. ret_code %d\n",ret_code);
      //return ret_code;
    }
  return Ks_para;
}

Can you help please if you have any idea ?

Thank in advance.
Best regards

 

[FrenchRiviera]

I want just to precise that in debug mode, I can see that the location
where I write changed but with wrong values.
For example, I'm writing 0x40228f5c to 04FC0000 address, but I can see
this :
04FC0000 2E479120 FFFFFFFF FFFFFFFF FFFFFFFF

I don't find an explication why.

Thanks in advance

 

[aruipksni]

I want just to precise that in debug mode, I can see that the location
where I write changed but with wrong values.
For example, I'm writing 0x40228f5c to 04FC0000 address, but I can see
this :
04FC0000 2E479120 FFFFFFFF FFFFFFFF FFFFFFFF

I don't find an explication why.

Thanks in advance

your data is shifted by 1 bit and endian swapped...

so you have after 1 bit shift 5c8f2240 ...
sh yo need you check why it is 1 bit shifted ....

 

[FrenchRiviera]

Thank you very much aruipksni for your answer, I will cheek why i have the endian swapped and the bit shift.
I let you know.

Best regards

 

[FrenchRiviera]

Hi again,

Just to inform you that i have always the same problem.
The behavior doesn't change even if use the alt_write_flash / alt_read_flash functions or alt_epcq_controller_write_block/alt_read_flash functions.

The routine that writes when using alt_write_flash is :
/* write to flash 32 bits at a time */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);

It's very strange. Do you have an idea what would be the problem?
Thank you in advance.
Best regards

 

[aruipksni]

Hi again,

Just to inform you that i have always the same problem.
The behavior doesn't change even if use the alt_write_flash / alt_read_flash functions or alt_epcq_controller_write_block/alt_read_flash functions.

The routine that writes when using alt_write_flash is :
/* write to flash 32 bits at a time */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);

It's very strange. Do you have an idea what would be the problem?
Thank you in advance.
Best regards

if you have constant 1 bit shift it strongly indicate that something is wrong in your
serial spi connection between the fpga and the flash device.
most likely 1 bit msb is not been read properly.

so i sugest that you should check it out.

 

[FrenchRiviera]

Ok, thank you. I will review the Quartus design configuration, maybe i made a mistake to configure pins between them together.

 

[ads-ee]

40 22 8F 5C - written data
5C 8F 22 40 - endian swapped
2E 47 91 20 - right shifted (when read back)

Well the data is being endian swapped first then shifted right between the time it is written and when its read, which means somewhere there are an incorrect number of serial shifts to load all the data being written or read back. Perhaps there is an extra register in the serial readback path, or you have a problem with the writes not shifting enough. Maybe you are transferring on the wrong clock edge? I'm pretty sure the EPCS has a SPI like transfer protocol, where outputs are on the falling edge and inputs are sampled on the rising edge. I also don't understand where the endian swap is coming from, you must have your EPCS interface hooked up incorrectly to the Nios-II system.

Have you tried running any simulations on the EPCS transfers? I'm pretty sure you should be able to unit test just the EPCS interface with an Avalon master BFM.

Looking at the EPCS device data sheet shows it shifts out from the MSB of a byte so the error must be on the translation from the 32-bit Nios-II Avalon interface to the byte shifting. The endian swap still throws me as the reads and writes should have been designed transparent to the endianess.

 

[FrenchRiviera]

Thank you ads-ee for answer. With my EPCS device i can boot both the FPGA configuration and Nios II software. I'm using the Quartus 15.0.When i add the EPCS controller, the DATA, DCLK, ASDI, and nCS signals are not exported to Nios entity. This is why in device and pin options, I configured them as shown in the picture joined, you find also the two other pictures that show the EPCS controller and the Nios configuration.
Best regards