Cyclone IV & 2xDDR2 connection : termination and power

[sebg]

Hi,

I am not very familiar with DDR components and I don’t want to miss anything or make errors in my design. I try to follow the cyclone III dev kit schematic (TPS51100 to generate Vref and Vtt for example) but it uses external terminations and I don't have much place on my board.

Components :
=> Altera Cyclone IV EP4CE30 (1 DDR <-> bank 3 & 4 // 1 DDR <-> bank 7 & 8)
=> 2xDDR2 MT47H32M16-25E

FPGA side :
VCCIO : +1.8V (bank3,4,7,8)
- rup2 : 49.9Ohm pull-up to +1.8V / rdn2 : 49.9Ohm pull-down to GND
- rup4 : 49.9Ohm pull-up to +1.8V / rdn4 : 49.9Ohm pull-down to GND
- point to point connected to DDR2 devices

Pinout parameters :
- IO standard = SSTL 18 class I
- output termination = series 50ohm with calibration (dq, dqs)
- assignment/timings verified by compilation

DDR2 controller parameters (HPC2) :
- memory drive strength setting = reduced
- memory ODT setting = 50 ohms
- memory format = discrete device

Do I miss something ?
Do I have to connect FPGA Vref IO (VREFBxNy) to DDR Vref (0.9V) ?
Do I have to add series resistor on ADDR / command signals and parallel resistor between differential ck/ck_n ?

Thanks for helping.
SG

 

[Sergey Bekrenyov]

Hello Sebg,

Any progress with your schematic?

Sergey

 

[sebg]

Hi Sergey,

With your advices I think I have finished my schematics (only decoupling left). So the DDR2 part is done.
My product manager have just decided to add a SATA interface on my board. So I think I will switch to cyclone IV GX family. I am considering the different option : commercial IP, developping from scratch...

Have a good day,

Sébastien.