Custom synthesis library for basic arithmetic operations

[Ebrahim Songhori]

Hi,

I am using Synopsys DC for synthesizing Verilog code to gate level netlist . I have designed a customized adder and I want it to be used where there is addition in my functional Verilog code, e.g.,

wire [N-1:0] a,b,c;
assign a = b + c;

Right now, it seems DC uses DW library by default. How to make synthesis library out of my adder and how to change the default to the new library?

Thanks,
Ebrahim

 

[artmalik]

Hi
Design Compiler has a cost function which depends on the area,performance, frequency..to achieve the optimal way. The custom adder which you have designed is not "better" than DW library implementation. Either you have to change the cost function of the dc_compiler(which is not recommended) or make a full adder better than DW implementation.
Thanks
Art Malike

 

[Ebrahim Songhori]

Thank you.

So, as I understand, if our customized adder results in better synthesis DC automatically choose our adder.

Just one more question: How can we change the objective function to only include area?

I want to generate a netlist for a non-hardware application. I am actually interested in minimizing area for a given Boolean function.

Thanks again,
Ebrahim

 

[artmalik]

You can always instantiate the "cell" in the RTL directly so the tool doesn't do any optimization. The design compiler will always try to make the design smaller within the timing constraints. The tool prefers to choose the cells it "understands", this way it can optimize the design properly if you want to change from one foundry to another or new technology. Letting the tool do its job has been the biggest winning factor because it is technology/constraint independent. That's why you will find less and less people making multi-bit adders ...and complex digital design is more for academics. The trend is to write "functionally correct Verilog" ---> "synthesize"--"P&R and Timing" with a generic library.