George_P
Member level 2
Hi,
I want to to configure RTL-Compiler (RC) to do the following while inserting clock gating:
- Calculate the "clock-enable" paths delays = dten
- For the enable paths that have a dten less than a threshold tthr, use library cell ICG1 and for the paths above tthr use library cell ICG2
Any idea if I can do that and how it's done? Does anyone know if Magma-Talus supports this?
Regards,
George
I want to to configure RTL-Compiler (RC) to do the following while inserting clock gating:
- Calculate the "clock-enable" paths delays = dten
- For the enable paths that have a dten less than a threshold tthr, use library cell ICG1 and for the paths above tthr use library cell ICG2
Any idea if I can do that and how it's done? Does anyone know if Magma-Talus supports this?
Regards,
George