The attached Sync Buck simulation (schematic also attached), has non symmetrical AC current in the CST , but there is very little build up of magnetising current in the secondary of the CST, due to the use of the diode bridge at the CST secondary. Therefore, would you agree that this circuit is fine?
-The secondary magnetising current merely has a 2mA DC level in it. (its saturation level is 52mA).
In fact, even a unipolar CST setup is fine (with only single rectifier diode in the CST secondary), but just has up to 20mA DC level in the secondary magnetising current, which is unwanted, but doesn’t saturate the EP13 (3C96) core, which, with 50 turns, would need the secondary magnetising current to go up to 52mA before saturation was caused.
Anyway, in the attached simulation , the secondary magnetising current is seen by putting “I(L28) + I(L27)/50” into the waveform window.
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In relation to the use of CST’s with synchronous Buck’s, the following article has called it totally wrong…………
Article:
**broken link removed**
Her is the duff quote from the above article (which concerns CSTs in sync Bucks)….
Alternatively, a current sense transformer can be exploited, but only if the current sense location is such that the current waveform is zero for part of the switching period to allow transformer reset, e.g. in series with the high-side FET.[unquote]
As I have prooven here, the synchronous buck has AC current in the CST when its in that location, and there is no zero current interval, and yet the CST operates perfectly fine, as long as a diode bridge is used in the secondary of the CST
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