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viyaaloth

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Hi all,

I am doing a custom design with Xilinx CPLD and xilinx FPGA. Now I am working with power requirements. I am using xilinx XC2C32A CPLD. I suppose to use 3.3V voltage as VCCIO and VCC=1.8V as voltage. But how can I get to know the maximum current rating for the corresponding voltages. What is meant by ICC(dynamic current) ?


voltage.PNGcurrent.PNG

Regards,
Viya
 

Hi,

The FPGA has two forms of current flowing through it: static current and dynamic current.

The static current is the current flowing while the device is not switching signal levels and is due to two circumstances
1-- the one that leaks through the FPGA just because it is powered up (no-load current).
2-- the one that flows through the input and output pins when they are loaded and are at steady-state.
You have two such current (ICCSB) listed for each output pin. Those flowing through the input pin are the leakage current listed as +/-1uA. Both of these currents are constant.

At the time that the FPGA is switching signal levels, an additional amount of current is drawn. This additional current due to switching effects is what is referred to as ICC(dynamic current). The more often switching occurs, the higher the dynamic current drawn. This is to say that this current varies with switching frequency.

For the maximum current rating for the I/Os, it depends on whether the I/O pin is configured as an input or an output. If it is configured as an input, then you do not have to worry about the current that would flow into that pin because the buffer associated with that pin will be activate and used, thereby allowing only the leakage current to flow through the pin. When the I/O pin is configured as an output, the current flowing through the pin would still be a leakage current if you are not using it in the open-collector or open-drain mode. If you are using it in the open-collector/-drain mode, then the maximum current would be provided in the FPGA datasheet. In the datasheet you provided, the recommendation is 2.5mA at 50 MHz. This recommendation is for the open-collector/-drain configuration. This means that you would use an appropriate pull-up resistor alongside your load at the output to limit the current to within 2.5mA (at the time of switching) if you are switching it at 50 Mhz. 0.25mA is listed for 1 MHz.

Hope this helps.
 
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