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current mode DC/DC loop-bandwidth guidelines ?

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hoonsk

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current loop bandwidth

Hi,
From word of mouth, I gather that for current mode DC/DC, the faster loop (inductor current sensing loop) bandwidth has to be at least 1/4 of the switching frequency and the outer loop (output voltage feedback) has to be even smaller than current sensing loop bandwidth (e.g.1/2) which makes it about 1/8 of fsw.
Can anyone comment or any documents that list out the requirements ?

Thanks,
Richard
 

v_c

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slup080

I think the general idea is that you don't want the loops to have the same bandwidth to avoid "fighting" between the current and the voltage loops. The outer voltage loop is made slower. This is reasonable, since this loop is trying to control the average value of the output voltage. So it does not have to respond to something within a switching period. The output of the voltage loop error amp is used as the reference for the inner current loop. This loop is made a little faster so it can responde a bit more quickly. In traditional current mode control, the switch current is sensed and when the switch current reaches a set level, the switch is turned off. So in this scheme, the controller is acting to limit the current in the switch. In making the inner current feedback loop faster, we are reducing the delay from the time the current in the switch is sensed to the time we recognize that the switch should be turned off.

The following are materials from the Unitrode Power Seminars. I think you should browse through them to see if it is what you want. Some of the documents are for current-mode control other are more general but they have section on CMC.

https://focus.ti.com/lit/ml/slup075/slup075.pdf
https://focus.ti.com/lit/ml/slup080/slup080.pdf
https://focus.ti.com/lit/ml/slup091/slup091.pdf
https://focus.ti.com/lit/ml/slup113a/slup113a.pdf
https://focus.ti.com/lit/ml/slup173/slup173.pdf

You can find more information at (look at the bottom of the page for Archived Unitrode Seminar Series)

https://focus.ti.com/general/docs/training/trainingevents.tsp?familyId=2

I hope that you find the material beneficial to your work.

Best regards,
v_c
 

hoonsk

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current share loop compensation

Thanks v_c.
So it sounds like the current mode control loop bandwidth is not necessary give rise to a wider bandwidth than voltage mode control. Some mentioned that current mode control is better because it has wider bandwidth and thus transient response is better...I've to re-think about it.
Does it mean that current mode control only has the main advantage of simplicity of compensation with 1/RoutCout pole to deal with ?

Thanks.
 

v_c

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dc-dc bandwidth

Advantages of current-mode control are easy loop compensation (this has to do with the 1/RC pole that you mentioned), some help with Right-Half-Plane problems (it does not eliminate them), ability to work with both CCM and DCM with good performance, and good line rejection.

Disadvantages are you have to sense current accurately, there is a subharmonic oscillation instability when you approach a 50% duty ratio, and poor signal to noise ratio on the current sense.

Most experienced designers agree that the most important thing to do in current-mode control design is to keep noise off the compensation ramp.

Three advantages of using current mode control which are:

1. Immune to input disturbance
It makes the supply look like a current source to the input therefore voltage changes at the input do not get through to the output.

2. Parallel current sharing
It is easier to parallel current sources into an output capacitor than parallel voltage sources.

3. Current protection
It is often implemented by cycle-by-cycle current limit protection of the power switch, making it immune to over-current damage from short circuited outputs or overloads.
 

hoonsk

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voltage loops

Thanks v_c.

"Most experienced designers agree that the most important thing to do in current-mode control design is to keep noise off the compensation ramp. "

I guess you mean the slope compensation block ? where is the source of noise ? is it the from the VDD ?
If we have an anti-double pulse block after the comparator, it should take care most of the noise business right ?

Thanks.
 

v_c

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slup080.pdf

Yes the slope compensation ramp. The circuit to generate it should be as noise immune as possible. What you are doing sounds right
 

lj053

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current mode dc/dc

hi V_C:
How to simulate the band width (close and open) with spectre or hspice. I think its so diff.
 

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