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[SOLVED] current mirror- mirroring current in more than 1 transistor

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Jun 30, 2014
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Hi all i know a simple current mirror where the current from one transistor is mirrored to the other. But i want to design a current mirror where i use 3 transistors and from 1 transistor i want the current to be mirrored to the other two. I'm working with NMOS so could someone please tell me the connections. For simple CM we just connect the drain to the gates of both the transistors. How am i supposed to give connection to the third transistor. I just tried connecting the gate of 3rd transistor to the gate of 1st transistor. (like all 3 transistor gates are now connected and which inturn to the drain of 1st transistor). Current is getting exactly mirrored in 2nd transistor but not in the 3rd. Could anyone pls help!!! Thank you!!!!

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I am a beginner to all this so i have not much idea. I read in current mirror circuit the current gets mirrored irrespective of the load. So is load a problem for my 3rd transistor???

if Vds is not equal, you won't mirror current equally.

Hi tony thanks for the link. I was able to find a link similar to that and was able to copy the current. But the thing is as mentioned in the link you gave as we add transistors i think the current like gets divided and the example in the link showed Ic1/2. I want to copy 30nA to my 2nd and 3rd transistor. I am able to copy 30nA from the 1st transistor to 2nd exactly. But in the 3rd transistor i am only getting 16nA. could you kindly tell me how can i get 30nA in the 3rd transistor as well. Thank you!!!

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And yes my VDS is not equal for 2nd and 3rd transistor. But i can't change that because i have connected the drains of both transistors to another circuit. Is der any way that i can adjust like say adding any resistor or anything. Because the VDS of 2nd transistor is high and that of the 3rd is low...

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But wen i use current mirror with two transistors i am able to mirror same current irrespective of VDS. After all isn't that what current mirror is supposed to do. I read in the book that it supplies steady current irrespective of the load. Pls correct me if i am wrong.

No the current is not divided. If the first transistor sinks 3 mA through its collector, every other transistor will EACH sink 3mA.

What happens is all the Vbe's are all the same (base emitter voltages) because they are all hard wired in parallel.
If the transistors all have exactly the same gain, all the collector currents must also be the same.

Whatever current is sunk by the first transistor, all the others will sink likewise.
It does work.

It works exactly the same with mosfets.
What I suspect is happening in your case is the mosfets are not well matched, and the gate thresholds are different enough to cause a significant current error.

Try fitting an identical 10 Meg resistor in each source. At 30nA that will drop 300mV. That should help balance things up a lot better.
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Vds is what determines the accuracy of the current mirroring when the Vgs are equal and the transistors are identical(i.e W and L of all the transistors are same and let the fingers ratio decide the current mirroring ratio). Then same Vds for all the transistors must result in same current without considering the mismatch effect.
In your case, you are able to get the expected current in the 2nd transistor but not in the 3rd transistor. Make sure that the Vds is the only problem for the 3rd transistor by connecting its drain to the same potential as the 1st transistor and seeing the expected current. If this is fine, then you have a Vds crunching effect. Try to increase the both W and L of your transistors (increases the area but betters the current mirroring).

transistor matched as in you mean by their length and width right??? I have all the 3 transistors of the same aspect ratio. And so wen the transistors are the same in length and width then for 180nm tech the Vth (threshold voltage) should be the same right? And gate threshold do u mean VGS. In the case of all 3 transistors i gave Gate connection to the current source and source of all 3 transistors are grounded. the VGS of all 3 nmos are the same. Only vds is differing in all 3. (i am using nmos) So where do you suggest to connect the resistor???

Also wen u say to connect drain of 3rd transistor to potential of 1st one do u mean i should give the drain connection to the drain of the 1st transistor??? The drain of the first transistor is connected to 30nA current source. I tried connecting drain of 3rd to drain of 1st which is to the current source and wen i do that 2nd and 3rd transistor are getting only 15nA. But on my own i tried to connect the drain of 3rd transistor to the drain of 2nd transistor and then all 3 transistors are now perferctly mirroring 30nA..

Initially vds for 1st, 2nd and 3rd were 336mV, 261mV and 20mV respectively. And the current copied were 30, 29 and 15. And my connections were for first transistor i gave current source to drain and gate, source of all 3 were grounded. For 2nd transistor drain to load and gate to gate of 1st nmos. 3rd drain to load and gate to gate of 1st transistor just like in the link. Now though i am able to copy the current as i am matching the vds of 2nd and 3rd nmos my overall circuit is giving me the wrong output. Its like i wish to change the vds for the 3rd transistor but then i cant mirror the current... i still don't get current mirror since wats the point if i have to adjust vds to mirror current. Irrespective of vds should the current mirror structure copy current. I am just learning the basics now so would just like to know what exactly it is.Thank you
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It all depends on what you are actually trying to do there.

If these are all individual discrete mosfets, as I initially assumed, how do you know all the gate thresholds and other characteristics are absolutely identical ?

The suggestion of fitting source resistors to each individual mosfet to provide local current feedback to each device is entirely sound and common practice for current mirrors where discrete devices are concerned.

If this is a design on a single silicon chip the situation is entirely different.
But as you are not telling us this, we can only guess at your purpose.

The solution to an on chip design problem then becomes entirely different.

The answer given by a previous poster to keep all the drain voltages the same is about the only practical solution, as fabricating 10 Meg resistors on a chip is going to be just a little bit impractical.

The solution is to turn each current sink into a cascode stage by adding an upper mosfet.
The upper mosfet will have all the gates common and fed from a fixed voltage source.
The sources of the upper cascode mosfets are connected to the drains of the lower mosfets.
Hence holding the lower devices drains all a the same fixed voltage.

The lower cascode half then becomes a true current source feeding the upper device, of which the drain voltage can vary hugely, having almost no effect on the programmed current.

Yes, I agree with Warpspeed. You can not have 20mv vds and get perfect mirroring. Because, the 3rd transistor is not in saturation. One of the things you can try is to cascode the current mirrors. But it will not solve the problem completely as the cascode transistor in the 3rd mirror will not be in saturation with just 20mV and nor will the main device be. You might see 20nA mirroring instead of 15nA, which is not what you want. Head rooms the transistors have are looking very low to go for cascoding.

For proper current mirroring to occur, the main device and the other devices Vds should be just about the same. If the first device has a Vds of 336mV, the mirroring devices should have Vds like at least 200mV to 500mV (enough to keep them in saturation, as in the case of 2nd transistor). In your case, it looks like the load connected to the 3rd transistor is very high resistance which is causing more voltage drop. What is the 3rd transistor actually connected to?

I meant to connect the drain of the 3rd transistor to a voltage source of value equal to the drain potential of the 1st transistor i.e 336mV to diagnose the problem. But the drain voltages you have mentioned clearly shows that the low Vds is the problem.

Oh i am working in cadence and yes it is an on chip design. Also i am not looking for the transistors to work in saturation. I want them to work in subthreshold region.

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