[SOLVED] Current mirror matching

[Junus2012]

Dear friends(especially Erikl )

I am trying to match the following MOS mirror , kindly suggest me a compact array according to common-centroied method please




Best Regards

 

[Junus2012]

Dear friends, before you suggest me, I have thought about this array

D E F X X X F E D
E F D D F E D F E
F D E A B C E D F
X F E B C A D X X
F D E C A B E D F
E F D D E F D F E
D E F X X X F E D

Where x is dummy transistor

how you find my array ????

 

[erikl]

Not too bad - but a nightmare for routing the layout. Hope this is a DC circuit, so routing symmetry isn't compulsory.

However: do you really need this 3:15 configuration? Wouldn't a 1:5 (or an even-numbered 2:10 , which is much easier to achieve regarding common centroid) configuration also be sufficient for your small-mismatch requirement?

In any case you need dummies around the whole array to guarantee a continuous environment also for the border devices, otherwise even a darned good common centroid symmetry would be useless.

 

[Junus2012]

Dear Erikl, I was looking forward for your reply to this post, in the same time I know German, the wochenende is a holy days for them

I have no problem at all to choose any value that give me K=5, by 10/2 or 5/1.

However I have chosen m =3 for the transistors A,B,C to match them together inside the the whole array. my supervisor told me this, it didnt come to mind that I can do it with 2 because they are three transistors. you just now told me and I thought about it to be like

ABC
CBA

Anyway, I have given the result of my schematic according to that division and I can not change it now, the important thing for me is that the array I have proposed is ok although you are saying not too bad...... it mean bad but if you take a look again to the array you find that all the variables are centred in the middle of array


Regarding the dummies, Mr. Erikl, in this case every array I have to surround with dummies from all sides.

Regarding the area of application, the first one is in the biasing circuit which is not effected by the routing or parasitic capacitance symmetries. but the second is in the current mirror amplifier that I am wary about.


Please if you have more suggestion specially about the array still I will also appreciate it, you are my layout teacher Sir

Not too bad - but a nightmare for routing the layout. Hope this is a DC circuit, so routing symmetry isn't compulsory.

However: do you really need this 3:15 configuration? Wouldn't a 1:5 (or an even-numbered 2:10 , which is much easier to achieve regarding common centroid) configuration also be sufficient for your small-mismatch requirement?

In any case you need dummies around the whole array to guarantee a continuous environment also for the border devices, otherwise even a darned good common centroid symmetry would be useless.

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I forget to tell, how could you match three transistor (A, B, C)with m=1 ????

 

[erikl]

... you are saying not too bad...... it mean bad

On the contrary: at least in Southern Germany (didn't you live there some time ago?) this rather means a good praise. If you say about a girl "she is not too ugly" this would mean she is rather good looking, a pretty girl. ;-)

how could you match three transistor (A, B, C)with m=1 ????

I think

DDDADD
EEBEEE
FFFCFF

... with dummies all around would be good enough. Not really common centroid, but saves a lot of Si real estate, and is much easier to be routed.

Would be interesting to compare MC mismatch (+ process) results of m=1, 2, and 3 layouts!

 

[Junus2012]

hahahaha, Erikl I am now sure you know me ..... not bad mean a less better than bad and the pretty is pretty

yes you are right about the complexity of the routing, but this is price you must pay when you use the common centroid method, and now I can not imagine a current mirror with for example 10 branches , however it is comin to my mind that for this case one cane mirror the current to another mirror then recover it back again with another mirror

please do you have any article about the effect of the non symmetry of the routing in general

On the contrary: at least in Southern Germany (didn't you live there some time ago?) this rather means a good praise. If you say about a girl "she is not too ugly" this would mean she is rather good looking, a pretty girl. ;-)


I think

DDDADD
EEBEEE
FFFCFF

... with dummies all around would be good enough. Not really common centroid, but saves a lot of Si real estate, and is much easier to be routed.

Would be interesting to compare MC mismatch (+ process) results of m=1, 2, and 3 layouts!

 

[erikl]

... one can mirror the current to another mirror then recover it back again with another mirror

Sure, but this could create the same mismatch inaccuracies!

... do you have any article about the effect of the non symmetry of the routing in general

No paper on this, sorry. But it's simple: the routing parasitics (for CMOS mainly the capacitive ones) contribute to the actual nodes' caps (output + input(s) caps), and by this can create different fan-out loads and - so - delays.

Same as with any other routing parasitics for connections which need symmetric delays. Not important for DC (bias) circuits, but essential for, e.g., CLK/CLKB distribution, fast buses, or converter switch-cap array routing.

 

[Junus2012]

Thank you very much erikl,

see you ;-)

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I just want a point to the non-symmetry routing... it leads to non uniform developed stress in the chip which degrade the reliability

Thank you very much erikl,

see you ;-)

 

[erikl]

... non-symmetry routing... it leads to non uniform developed stress in the chip which degrade the reliability

Not at all - at least to my knowledge. I couldn't imagine any stress effect on the semiconductor crystal lattice due to non-uniform routing.

 

[Junus2012]

Hello erikl

Kindly refer to this paper, here is something about the stress

by the way I just remembered another these question,

1. does the routing over the transistors (except the gate area which is not recommended to route over it) contribute to the transistors mismatch ???

me I am thinking that since the routing is not in the active area where the transistors are, and because it isolated from the transistors with a thick oxide then it will not effect the matching

2. is it possible to use the metal 3 for any routing ???

Thank you in advance

 

[erikl]

Kindly refer to this paper, here is something about the stress

Where did you hide it? ;-)

1. does the routing over the transistors (except the gate area which is not recommended to route over it) contribute to the transistors mismatch ???
... I am thinking that since the routing is not in the active area where the transistors are, and because it isolated from the transistors with a thick oxide then it will not effect the matching

If you are not routing over the active area but over thick oxide, you're not routing over transistors! And then it shouldn't affect the transistor mismatch, of course.

2. is it possible to use the metal 3 for any routing ???

Sure, why not?

 

[Junus2012]

I am sorry I forgot it

here

**broken link removed**

for metal 3 question I dont remember where I read it used only for VDD and ground connections,

 

[erikl]

**broken link removed**

I've got no access to IEEE papers any more, sorry. Non-uniform metal coverage of course may create stress on silicon, but primarily has nothing in common with non-uniform routing lengths.

for metal 3 question I dont remember where I read it used only for VDD and ground connections

May be, depending on available number of metal layers, but then not necessarily limited to power supply routing.

 

[Junus2012]

take it, it is available for free in google

 

[Junus2012]

Hello Erikl

Kindly what is the floorplanning function ???. I finished complete 5 layout circuits and the teacher never told me to use it

 

[erikl]

take it, it is available for free in google

Thank you. But still:

Non-uniform metal coverage of course may create stress on silicon, but primarily has nothing in common with non-uniform routing lengths.

what is the floorplanning function ???

I don't know for sure, but I'd think your teacher means the cost of the layout, which includes both the effort to create and verify it, and the cost of parasitics and silicon area - all this seen in terms of achieved mismatch reduction in comparison to the simplest execution (1:5 in your case).

Or, it could simply mean: "Don't exaggerate!" (no harm meant).

 

[Junus2012]

hahahaha, it is ok


Erikl, perhaps I will use this post for further layout questions in the future, is it ok ?

Thank you. But still:


I don't know for sure, but I'd think your teacher means the cost of the layout, which includes both the effort to create and verify it, and the cost of parasitics and silicon area - all this seen in terms of achieved mismatch reduction in comparison to the simplest execution (1:5 in your case).

Or, it could simply mean: "Don't exaggerate!" (no harm meant).

 

[AMSVJ]

is it not problem to match a MOS(D E F) in a single row, as u said..

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Where did you hide it? ;-)


If you are not routing over the active area but over thick oxide, you're not routing over transistors! And then it shouldn't affect the transistor mismatch, of course.

Sure, why not?

I am not clear with that thick oxide in layout.
And how it isolates metals when not routed over the MOS.

 

[gradha]

I have tried u r schematic(circuit) in the Auto place and Route . And tool has generated this pattern
E F D E F X X
D E F D E F D
F D E F D E F
E F D E F D E
D E F D E F D
C D E F D E F
B C D E F A B
A B C D E F A

The above pattern is for 8 rows.

Hope this will help.