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Current mirror matching and layout doubts

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brxnet

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Hi,
I am new to analog layout ,I am working in Cadence.
I want to make matching layout for current mirror consisted of two identical mosfets, 240/0.7um.I am planing to make 4 mosfets of 60/0.7um of each mosfet in mirror,and then to use 1D common centroid. In Art of analog layout from Alan Hastings i found interdigitalized pattern
dAsBdBsAdAsBdBsAd (mosfets are called A and B,d-drain,s-source)
I looked in lots of books and tutorials on the net,this pattern is widely used,in Art of analog layout is also mentioned as one of the best for interdigitization.But since there isn't same number of drains for A and B mosfet(A has 4 drains and B 3),then I guess thas this is good matching for DC,but not for AC since their parasitic capacitance are quite different with this patter.Am I right?
With what patter can I get better matching of parasitic capacitances,can I use
dAsBd dBsAdAsBd dBsAd
It is also from Alan Hastings where he mentions that this patter is with smaller compactness then previous,but with gaps between mosfets B enables me to get same number of drains.But if I do that,how wide should the gaps be to get identical parasitic capacitances, what about the dummies,should I put them on the start and in the end of the pattern,and in gaps also or what?
Is there some better pattern which i could use?
I know that 2D common centroid is supperior,
dAsBdBsAd
dBsAdAsBs
this pattern enables me to have same number of drains,but I am afraid that because of more complicated routing,i wont be able to make symmetrical wire routing,how much will that affect matching?
Would appreciate your thoughts..Thanks!
 

BigBoss

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Parasitic Capacitance does not have a high priority against matching in DC or LF signal circuits such as current sources,mirrors,LF amplifiers etc.Matching is more important here.
 

t4_v

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Hi brxnet,

First of all, your transistors are big thus their matching should be improved just by that. The problem can be the length that I guess is the minimum length and is equal to 0.7 um, thus it can be a little problematic in Monte Carlo and the matching can worsen.

Secondly, your example ABBAABBA is, using Baker book, rather common centroid. Interdigitated layout is ABABABAB.
Take a look also here: http://www.ece.utah.edu/~harrison/ece5720/Common_Centroid.pdf .

Thirdly, as BigBoss pointed out parasitic capacitances are not so important. The currents that flow through transistors depends on their dimensions (width W and length L). The most important is that the two transistors dimensions are the same, thus in layout is usually means bigger than minimum sizes and the same surroundings for both transistors.
 
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brxnet

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Hi t4_v,thank you for your reply.

First of all, your transistors are big thus their matching should be improved just by that. The problem can be the length that I guess is the minimum length and is equal to 0.7 um, thus it can be a little problematic in Monte Carlo and the matching can worsen.[/QUOTE]
My technology is 0.35um, I choose 0.7u to improve matching,i understand that for better matching length have to be as large as possible(even when width is already large),but I don't know is there some kind of rule of thumb what is minimal length for good matching?

Secondly, your example ABBAABBA is, using Baker book, rather common centroid. Interdigitated layout is ABABABAB.
Take a look also here: http://www.ece.utah.edu/~harrison/ece5720/Common_Centroid.pdf .
About ABABABAB,how much can this type of layout be good for marching,since it does not have same common centre for both mosfets.[/QUOTE]
Also,is multi-finger layout of common centroid (like in pdf you send,section Common Centroid Layout with Multi-Fingered Gates) good technique for matching,can I just take my mosfets A and B ,divide each of them in two smaller mosfets with multfinger and make common centroid layout?or is it much better to make interdigitated common centroid layout?

Thirdly, as BigBoss pointed out parasitic capacitances are not so important. The currents that flow through transistors depends on their dimensions (width W and length L). The most important is that the two transistors dimensions are the same, thus in layout is usually means bigger than minimum sizes and the same surroundings for both transistors.[/QUOTE]
I am making full differential opamp,in which i need current mirrors and diff pair of mosfet,I made some initial simulations and I noticed that when I tried patterns which don't have same parasitic capacitances, I dont have symmetrical outputs,so I think that for my circuit I need to have as much as possible symmetrical parasitic capacitances.
 

t4_v

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Hi brxnet!

Sorry for the late reply.

Here are answers:

1) The rule of thumb is: "in order to have a good matching, transistors should NOT have minimum dimensions". If 0.7 is minimum length Lmin, the length two times larger is 1.4 um. But I would try first with 1.5 Lmin, that is 1.05 um. If matching is still not what we want, then I would go with 1.4 um.
0.35 um should be a cheap technology, so larger dimensions are not painful. Usually, designers keep minimum lengths due to two reasons: speed and price. The shorter the transistor, the faster it is. The smaller the transistor the smaller chip area and thus lower price for the chip.

2) Full common centroid (horizontal and vertical, not just ABBAABBA) is in theory the best. However, in practice it can be troublesome due to for example routing metal paths. Thus, usually ABBAABBA or ABABABAB is used as their are easier to layout and provide good properties.
You can due whatever you want with your transistors, divide them on as many sub-transistors as you want and create as many fingers as you want. Common Centroid Layout with Multi-Fingered Gates is used for wide transistors. Transistors are closer to each other, series resistance is reduced, parasitic capacitance to bulk can be reduced. However, I would not complicate the layout. I would just layout it in the easiest way for you and then see the properties of the circuit. If they should be better, then play with the layout.

3) Yes, you're right. If you make high-speed fully differential opamp, then a lot of things come into play. Remember when you use big resistors, then you have bigger parasitics. Thus, try to increase current is you are not satisfied with the circuit performace.
By "symmetrical outputs" you mean, AC behavior of the opamp when AC input signals are applied?
 

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