current mirror layout and biasing condition

Status
Not open for further replies.
W

whlinfei

Member level 2
Joined
Dec 31, 2008
Messages
48
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,658
Hi all,

I am using several current mirrors in my design, with 1uA as one unit.

I am not sure about the transistor size that I should use.
Is that any normal standard for the ratio of Vds(eff) over Vth to maintain to keep the biasing stable.

p.s. in the simulation there is no problem, every current mirror in saturation region. but I am gonna fabricate this chip, I am not sure if it will have some problem.
I use 0.13 IBM process.
 

Hello Whlinfei,

The amount of Vds(eff), lets say Overdrive depends on your design. If its just a standard not so fast design i would say anything from 100mV to 150mV is perfect. It depends if you are doing alot of cascoding... If it has to be fast you should us more, 150mV to 250mV.
Since I do not know what you are designing, you need to decide....
 

Run some corner simulation or monte carlo to verify it further.
 

Hi,

Thank you for your reply.
I am using 1.4V power supply and normal FET I use have a Vth around 0.2V for NMOS.

The speed is not an issue for me as a delay around 80ns is fine for my design.

May I know the reference that you have come across on this issue ? So I could get a more comprehensive understanding on this one ?

thank you so much.

Best Regards,
Linfei
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…