The attached files illustrate the points mentioned. The top layer ground plane ( green) provides the localised switching loop return, the vias linking this segmented ground area to the main contiguous ground plane. The vias also provide thermal relief for the controlling IC, this design is from a few years ago, these days I would use thermal vias directly under the controller and have them capped. Having done some thorough thermal investigations of some design recently, after the main FPGA's, micro's etc the on board SMPS controllers were the next hottest thing. (We'll leave thermal management for another day
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The other main points illustrated are:
Under the main noisy switching node the ground and power copper has been cleared to minimise capacitive coupling of the high frequency harmonics.
The feedback components are away from the noisy part of the circuit, and the feedback is taken from a point away from the SMPS and the quite side of the output capacitor.
The input, output and switching node tracks are exactly the right size, and the signals are guided through the respective input and output capacitors. This again minimises the amount of coupling the supply will have with any other circuitry.
This design is an extreme example of a simple SMPS design, that was done in conjunction with National Semi to minimise EMC issues with having multiple cascaded SMPS's on some boards, I now use it as a standard guideline for all our SMPS designs.
I also did a few large SMPS designs (200W upwards), which were fun, but I can't find the documentation at the moment, but the principles were the same just on a larger scale.