Current density - regarding different metals

[sridhartv25]

Current density

Hello all,

1. Why do metals have lower current capability when thay cross oxide steps.
What is this oxide steps , (is it field oxide).

2. Why the higher order metals has more current rating than the lower order metals for a given width.

Regards,
Sridhar.

 

[deepak242003]

Re: Current density

Hello all,



2. Why the higher order metals has more current rating than the lower order metals for a given width.

Regards,
Sridhar.

cause of more thickness..

 

[dick_freebird]

What do you mean, higher order metals?

 

[keith1200rs]

What do you mean, higher order metals?

I would guess he is referring to 'nearer the top surface of the chip' where metal is often thicker. I don't know if surface heat dissipation is also better with metal closer to the surface?

Keith

 

[deepak242003]

I would guess he is referring to 'nearer the top surface of the chip' where metal is often thicker. I don't know if surface heat dissipation is also better with metal closer to the surface?

Keith

In this case we can say it should have more dissipation capability..for thick metals as compared to lower metals..

let me know ur views.

Deepak

 

[keith1200rs]

In this case we can say it should have more dissipation capability..for thick metals as compared to lower metals..

let me know ur views.

Deepak

In theory, the allowed dissipation could be higher with the higher metals, but I think the allowed metal current densities are set by metal migration limitations rather than power. It is tricky to compare because metal1 is usually the thinnest and the top metal often thicker. Also, the foundries may change the composition of the metal on different layers (mix of Al, Ti and TiN) so a comparison can be difficult.

Keith.

 

[dick_freebird]

If your die is attached at the backside then lower layers
have a shorter thermal path. If flip-chip then the opposite.

Metal composition is a significant factor in EM resistance
(allowable A/cm2).

Power dissipation per se is never the problem for reliability.
However badly run electromigration tests, which do not factor
in self-heating, can result in bogus design rules.

Attempting to generalize a reason, is not going to get you
anywhere. The foundry reliability folks make the rules
and you get to love it or leave it.

 

[frankliner]

Addressing 1.

Most newer processes are planarized so you don't need to worry about differences in oxide thicknesses.

0.35 and lower technologies are usually planarized. The metalization looks like:
**broken link removed**

For older processes the upper levels have much more variation in the z axis. This difference in topology leads to the requirement of thicker metal with more spacing in between for each upper layer metal. It is impossible to keep the metal thickness uniform when there are changes in the z axis. This produces thinner spots when metal transitions from different oxide areas. This can be low voltage oxide, high voltage oxide, field oxide, and maybe more. This could lead to design rules with different current densities depending on whether the line crosses different oxide areas. Without planarization you see:
http://www.nxp.com/news/backgrounders/bg9809/images/bg9809-1.gif

 

[keith1200rs]

You second picture is more what I am used to seeing! Useful explanation, thanks.

Keith.

 

[dick_freebird]

Many planarized processes use plug vias. These can reduce
the overall electromigration resistance if the via is not the
same metal as the conductor layer, because the via will not
be a "makeup source" of material as electromigration proceeds.
You may see this as a via rule that's unusually low current
density, or you may see it misassigned to the conducting
layer depending on whether the person doing the test and
analysis has a good picture of what's really failing.

A proper current density analysis will use the worst case
metal thickness, which will include whatever you know about
thinning over topography. In nonplanarized processes there
can be stackup effects, such as Met3 traversing a coincident
M1 and M2 edge will have worse coverage than Met3 crossing
Met2 alone. Your layout style, if you're doing it by hand,
might try to offset edges and so on if you're doing either
high-rel or highly stressed (cheaping out on conductor
width so you can be a die-size hero) designs.

 

[sridhartv25]

Hello friends,

Thanks alot for your answers and I could understand that increased current density for the top metal layers is because of increased thickness , I could see this in the process document.

Regards,
Sridhar.