ctype-stubs_32.a No such file or directory

[ali kotb]

hello ALL
I use vcs program from synopsys for verilog code compilation on redhat5

I am designing a digital filter in behavioral verilog "CIC.v" and it's test bench is "test_CIC.v" using vlogan, vcs,dve.
vlogan went great, the problem is with vcs command , I got this error
"g++:/home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a:No such file or directory"

*******************************************************************************************
terminal
*****************************************************
[root@localhost ~]# cd /home/synopsys/
[root@localhost synopsys]# source .bash_profile
[root@localhost ~]# cd Synopsys_Installed/VCS-mx/bin/
[root@localhost bin]# ./vlogan /home/synopsys/decimation/testCIC.v /home/synopsys/decimation/CIC.v
Chronologic VCS (TM)
Version G-2012.09_Full64 -- Mon Jun 24 14:28:07 2013
Copyright (c) 1991-2012 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/home/synopsys/decimation/testCIC.v'
Parsing design file '/home/synopsys/decimation/CIC.v'
CPU time: .069 seconds to compile

[root@localhost bin]# ./vcs /home/synopsys/decimation/testCIC.v /home/synopsys/decimation/CIC.v
Chronologic VCS (TM)
Version G-2012.09_Full64 -- Mon Jun 24 14:28:10 2013
Copyright (c) 1991-2012 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/home/synopsys/decimation/testCIC.v'
Parsing design file '/home/synopsys/decimation/CIC.v'
Top Level Modules:
testCIC
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -melf_i386 -Wl,-whole-archive -Wl,-no-whole-archive SIM_l.o 5NrI_d.o 5NrIB_d.o pre_vcsobj_1_1.o rmapats_mop.o rmapats.o /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libnplex_stub.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libvirsim.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/liberrorinf.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libsnpsmalloc.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libvcsnew.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libuclinative.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/vcs_save_restore_new.o /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
g++: /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a: No such file or directory
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .143 seconds to compile + .024 seconds to elab + .022 seconds to link
[root@localhost bin]#


can u please help me

 

[jaynarayan]

hello ALL
I use vcs program from synopsys for verilog code compilation on redhat5

I am designing a digital filter in behavioral verilog "CIC.v" and it's test bench is "test_CIC.v" using vlogan, vcs,dve.
vlogan went great, the problem is with vcs command , I got this error
"g++:/home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a:No such file or directory"

*******************************************************************************************
terminal
*****************************************************
[root@localhost ~]# cd /home/synopsys/
[root@localhost synopsys]# source .bash_profile
[root@localhost ~]# cd Synopsys_Installed/VCS-mx/bin/
[root@localhost bin]# ./vlogan /home/synopsys/decimation/testCIC.v /home/synopsys/decimation/CIC.v
Chronologic VCS (TM)
Version G-2012.09_Full64 -- Mon Jun 24 14:28:07 2013
Copyright (c) 1991-2012 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/home/synopsys/decimation/testCIC.v'
Parsing design file '/home/synopsys/decimation/CIC.v'
CPU time: .069 seconds to compile

[root@localhost bin]# ./vcs /home/synopsys/decimation/testCIC.v /home/synopsys/decimation/CIC.v
Chronologic VCS (TM)
Version G-2012.09_Full64 -- Mon Jun 24 14:28:10 2013
Copyright (c) 1991-2012 by Synopsys Inc.
ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file '/home/synopsys/decimation/testCIC.v'
Parsing design file '/home/synopsys/decimation/CIC.v'
Top Level Modules:
testCIC
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -melf_i386 -Wl,-whole-archive -Wl,-no-whole-archive SIM_l.o 5NrI_d.o 5NrIB_d.o pre_vcsobj_1_1.o rmapats_mop.o rmapats.o /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libnplex_stub.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libvirsim.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/liberrorinf.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libsnpsmalloc.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libvcsnew.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/libuclinative.so /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/vcs_save_restore_new.o /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
g++: /home/synopsys/Synopsys_Installed/VCS-mx/linux/lib/ctype-stubs_32.a: No such file or directory
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .143 seconds to compile + .024 seconds to elab + .022 seconds to link
[root@localhost bin]#

can u please help me

------------------------------------

This error comes due to 32/64 bit machine type. So if your using 64 bit version then run vcs with -full64 option

vcs file.v testbench.v -full64 otheroption

I hope this will solve your problem

------------------------------------------------------------

 

[ali kotb]

Yes, It is solved
thank u