Hi,
I don't know which tool you used.
I want to know, why to declare two clocks, the test clock include all system clock domain ?, you need to define the clock that include all clocking element, and the second one will automaticly equilibrated.
for example:
system clock source comes from an analog module.
test clock source comes from a pad.
both clocks are connected to a mux that selecte the test clock only in test mode and the system clock only in functionnal mode.
In this case, you can define only one clock source, from the mux output, and both clock tree will be equivalent. Only the latency could be different between the two clocks source (pad or analog module), but the design will correctly working.