Did you want to use 40 MHz for some external bus clocking?
If yes you may add a RC on a clock net (but not on a oscilator) circuit to increase fall and rise time of clock signal. It will decrease higher harmonics of the clock signal.
Hello
So you may implement shielding of clock net and oscillator. I mean ground plane under and copper plane nearby the crysta connected together through viasl. It's should be enough.